Technical Product Specification

Intel
®
Server Board S5400SF TPS Functional Architecture
Revision 2.02
Intel order number: D92944-007
25
3.2.3.4 Memory upgrades
The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must cover the
same slot position on both channels. DIMMs pairs must be identical with respect to size, speed,
and organization. DIMMs that cover adjacent slot positions do not need to be identical.
When adding two DIMMs to the configuration shown in Figure 8, the DIMMs should be
populated in DIMM slots C1 and D1 as shown in the following figure:
AF002166
Branch 0 Branch 1
Channel A Channel D
Channel B Channel C
Figure 9. Recommended Four-DIMM Configuration
Functionally, DIMM slots A2 and B2 could also be populated instead of DIMM slots C1 and D1.
However, the system does not achieve equivalent performance. The above figure shows the
supported DIMM configuration that is recommended because it allows both memory branches
from the MCH to operate independently and simultaneously. Memory bandwidth is doubled
when both branches operate in parallel.
3.2.3.5 ECC Code Support
When branches operate in the dual-channel mode, the MCH supports the 18 device DRAM
failure correction code (SDDC aka SECC) option for FBD. As applied by the MCH, this code has
the following properties:
 Correction of any x4 or x8 DRAM device failure
 Detection of 99.986% of all single bit failures that occur in addition to a x8 DRAM failure.
The MCH detects a series of failures on a specific DRAM and uses this information in
addition to the information provided by the code to achieve 100% detection of these
cases.
 Detection of all two wire faults on the DIMMs. This includes any pair of single bit errors.
 Detection of all permutations of 2 x4 DRAM failures.