Technical Product Specification

Functional Architecture Intel
®
Server Board S5400SF TPS
Revision 2.02
Intel order number: D92944-007
20
 The Snoop Filter lookup latency is four SF-clocks or two MCH core clocks to support
single snoop stall in an idle condition (single request issued from either bus). If both
buses make requests simultaneously, the snoop-filter always selects bus 0 first. In such
a scenario, bus 0 request has one snoop-stall and bus 1 request has two snoop-stalls.
 Active Way/Invalid/E/M/Pseudo-Random replacement algorithm with updates on lookups
and invalidates; Invalid/Pseudo-Random replacement algorithm with updates on lookups
and invalidates.
 Tag entries support a 38-bit physical address space. The MCH supports an external
address space of 38 bits as well.
 ECC coverage with correction of single bit errors and detection of double bit errors
(SEC-DED).
- Invalid/Random Array does not implement ECC or parity protection. A bit failure
results in the selection of the wrong victim entry and may have a minimal impact on
performance. However, the coherency engine resolves the conflict and guarantee
correctness.
3.2.3 System Memory Controller and Memory Subsystem
The MCH masters four fully buffered DIMM (FBDIMM) memory channels. The four memory
channels are organized in to two branches. Each branch is supported by a separate memory
controller. The two channels on each branch operate in lock step to increase FBD bandwidth. A
branch transfers 16 bytes of payload/frame on Southbound lanes and 32 bytes of payload/frame
on Northbound lanes.
The host frequency is the speed of the memory interface of the Intel
®
5400 Chipset. This
frequency determines the speed at which the chipset completes a memory transaction. The
gear ratio determines the relative speed between the processor interface and the memory
interface. The BIOS supports 667 MHz and 800 MHz FB-DIMMs, and automatically selects and
configures the host frequency and gear ratio.
The following table shows the theoretical peak bandwidth of the Front-Side Bus and Memory
Bus when the server board is configured with supported processor and memory configurations.
Table 6. Front-Side Bus and Memory Bus Bandwidth
FSB Clock (Quad
pumped)
FSB Transfer
Rate
FSB BW FBD Channel
Frequency
DRAM Clock DRAM Transfer
Rate
FBD BW per
Branch
266 MHz
(1066 MHz)
1066 MT/s 8 GB/s 3.2 GHz 266 MHz 533 MT/s 8.4 GB/s
4 GHz 333 MHz 667 MT/s 10.6 GB/s
333 MHz
(1333 MHz)
1333 MT/s 10.7 GB/s 3.2 GHz 266 MHz 533 MT/s 8.4 GB/s
4 GHz 333 MHz 667 MT/s 10.6 GB/s
400 MHz
(1600 MHz)
1600 MT/s 12.8 GB/s 3.2 GHz 266 MHz 533 MT/s 8.4 GB/s
4 GHz 320 MHz
640 MT/s
1
10.2 GB/s
4.8 GHz 400 MHz 800 MT/s 12.8 GB/s
1
In system configurations that utilize processors supporting a 1600 MHz FSB and 667 MHz FBDIMMs concurrently,
the actual DRAM transer rate is 640 MT/s due to a set gear ratio inside the MCH.