Technical Product Specification

Intel
®
Server Board S5400SF TPS Table of Contents
Revision 2.02
Intel order number: D92944-007
iii
Table of Contents
1. Introduction ..........................................................................................................................1
1.1 Chapter Outline........................................................................................................ 1
1.2 Server Board Use Disclaimer .................................................................................. 1
2. Product Overview.................................................................................................................3
2.1 Intel
®
Server Board S5400SF Feature Set .............................................................. 3
2.2 Server Board Layout................................................................................................ 4
2.3 Connector and Component Locations ..................................................................... 5
2.4 Intel
®
Light-Guided Diagnostics LED Locations....................................................... 7
2.5 External I/O Connector Locations............................................................................ 8
3. Functional Architecture.......................................................................................................9
3.1 Processor Support ................................................................................................. 10
3.1.1 Processor Population Rules .................................................................................. 13
3.1.2 Multiple Processor Initialization ............................................................................. 15
3.1.3 Enhanced Intel SpeedStep
®
Technology............................................................... 15
3.1.4 Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) ....................................... 15
3.1.5 Execute Disable Bit Feature .................................................................................. 16
3.1.6 Multi-Core Processor Support ...............................................................................16
3.1.7 Intel
®
Virtualization Technology ............................................................................. 16
3.1.8 Platform Environmental Control Interface (PECI) .................................................. 17
3.1.9 Common Enabling Kit (CEK) Design Support........................................................ 17
3.2 Intel
®
5400 Memory Controller Hub Chipset (Intel
®
5400 MCH Chipset)............... 18
3.2.1 Processor Front-Side Buses.................................................................................. 19
3.2.2 Snoop Filter ........................................................................................................... 19
3.2.3 System Memory Controller and Memory Subsystem............................................. 20
3.2.3.1 Supported Memory............................................................................................. 21
3.2.3.2 DIMM Population Rules and Supported DIMM Configurations .......................... 23
3.2.3.3 Minimum Memory Configuration ........................................................................ 24
3.2.3.4 Memory upgrades .............................................................................................. 25
3.2.3.5 ECC Code Support............................................................................................. 25
3.2.3.6 Memory Sparing................................................................................................. 26
3.2.3.7 FBD Memory Thermal Management .................................................................. 27
3.2.3.8 BIOS Support of Memory Subsystem ................................................................ 27
3.2.3.8.1 Memory sizing and Configuration ................................................................. 27
3.2.3.8.2 POST Error Codes........................................................................................ 27
3.2.3.8.3 Publishing System Memory .......................................................................... 28