Technical Product Specification

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Intel

Server Board S5400SF

Technical Product Specification

Intel order number: D92944-007

Revision 2.02

May 2010

Enterprise Platforms and Services Division - Marketing

Summary of content (189 pages)

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Intel® Server Board S5400SF Technical Product Specification Intel order number: D92944-007 Revision 2.
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Revision History Intel® Server Board S5400SF TPS Revision History Date Revision Number Modifications September 2007 1.00 Initial release. July 2008 2.00 August 2008 2.01 Updated processor naming. May 2010 2.02 Deleted CCC and CNCA. Updated supported CPU table. Added memory type support table. Updated password clear procedure. Updated supported BIOS POST error code table. Updated BIOS Setup Utility options section.
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Intel® Server Board S5400SF TPS Table of Contents Table of Contents 1. 2. 3. Introduction .......................................................................................................................... 1 1.1 Chapter Outline........................................................................................................ 1 1.2 Server Board Use Disclaimer .................................................................................. 1 Product Overview.............................
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Table of Contents Intel® Server Board S5400SF TPS 3.2.3.8.4 Memory Interleaving .................................................................................... 29 3.2.3.8.5 Support for Mixed Speed Memory Modules................................................. 29 3.2.3.9 Memory Error Handing ....................................................................................... 29 3.2.3.9.1 Faulty FBDIMMs ...........................................................................................
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Intel® Server Board S5400SF TPS 3.5.2 Video Memory Interface......................................................................................... 41 3.5.3 Dual Video ............................................................................................................. 41 3.6 Network Interface Controller (NIC) ........................................................................ 42 3.6.1 Intel® I/O Acceleration Technology .................................................................
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Table of Contents Intel® Server Board S5400SF TPS 4.4.4.1 Chassis Intrusion................................................................................................ 56 4.4.4.2 Reset Button ...................................................................................................... 56 4.4.4.3 Diagnostic Interrupt (Front Panel NMI)............................................................... 56 4.4.4.4 Chassis Identify.......................................................................
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Intel® Server Board S5400SF TPS 4.16.2 Processor VRD Over-temperature Sensor ............................................................ 70 4.16.3 ThermalTrip Monitoring.......................................................................................... 70 4.16.4 Internal Error (IERR) Monitoring ............................................................................ 71 4.16.5 Dynamic Processor Voltage Monitoring................................................................. 71 4.16.
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Table of Contents 5.2.3.9 Intel® Server Board S5400SF TPS 5.3 Exit Screen ....................................................................................................... 108 Loading BIOS Defaults ........................................................................................ 110 5.4 Rolling BIOS ........................................................................................................ 110 5.4.1 BIOS Select Jumper in Normal Mode (Jumper pins 2-3 connected) .............
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Intel® Server Board S5400SF TPS 7. 6.8 Fan Headers ........................................................................................................ 131 6.9 Chassis Intrusion Switch Header......................................................................... 132 Jumper Block Settings .................................................................................................... 133 7.1 8. Recovery Jumper Blocks ..........................................................................
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Table of Contents Intel® Server Board S5400SF TPS 10. Regulatory and Certification Information....................................................................... 152 10.1 Product Regulatory Compliance .......................................................................... 152 10.1.1 Product Safety Compliance ................................................................................. 152 10.1.2 Product EMC Compliance – Class A Compliance ...............................................
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Intel® Server Board S5400SF TPS List of Figures List of Figures Figure 1. Server Board Layout...................................................................................................... 4 Figure 2. Components and Connector Location Diagram............................................................. 5 Figure 3. Intel Light-Guided Diagnostics LED Location Diagram ................................................ 7 Figure 4. Intel® Server Board S5400SF External I/O Layout ..........................
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List of Figures Intel® Server Board S5400SF TPS Figure 33. Setup Utility — Hard Disk Order Screen Display ..................................................... 104 Figure 34. Setup Utility — CDROM Order Screen Display ....................................................... 105 Figure 35. Setup Utility — Floppy Order Screen Display .......................................................... 105 Figure 36. Setup Utility — Network Device Order Screen Display............................................
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Intel® Server Board S5400SF TPS List of Tables List of Tables Table 1. Major Components and Connectors ............................................................................... 6 Table 2. Processor Support Matrix ............................................................................................. 13 Table 3. Mixed Processor Configurations ................................................................................... 14 Table 4. Intel® EM64T Operating Modes .............................
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List of Tables Intel® Server Board S5400SF TPS Table 33. Setup Utility — Memory Configuration Screen Fields ................................................. 86 Table 34. Setup Utility — Configure RAS and Performance Screen Fields................................ 87 Table 35. Setup Utility — ATA Controller Configuration Screen Fields ...................................... 89 Table 36. Setup Utility — Mass Storage Controller Configuration Screen Fields ....................... 91 Table 37.
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Intel® Server Board S5400SF TPS List of Tables Table 68. VGA Connector Pin-out (J6A1)................................................................................. 126 Table 69. RJ-45 10/100/1000 NIC Connector Pin-out (JA8A1, JA8A2).................................... 127 Table 70. 44-pin IDE Connector Pin-out (J3G2) ....................................................................... 127 Table 71. 50-pin Intel® I/O Expansion Module Connector Pin-out (J3B1).................................
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List of Tables Intel® Server Board S5400SF TPS < This page intentionally left blank. > xvi Revision 2.
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Intel® Server Board S5400SF TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board-specific information detailing the features, functionality, and high-level architecture of the Intel® Server Board S5400SF. In addition, design level information for specific subsystems can be obtained by ordering the External Product Specifications (EPS) or External Design Specifications (EDS) for a given subsystem. EPS and EDS documents are not publicly available.
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Introduction Intel® Server Board S5400SF TPS determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. 2 Revision 2.
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Intel® Server Board S5400SF TPS 2. Product Overview Product Overview The Intel® Server Board S5400SF is a monolithic printed circuit board with features that were designed to support the high-density High Performance Computing (HPC) server market. 2.1 Intel® Server Board S5400SF Feature Set Feature Description Processors 771-pin LGA sockets supporting one or two Intel® Xeon® processors Memory 16 Keyed DIMM slots supporting fully buffered DIMM technology (FBDIMM) memory.
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Product Overview 2.2 Intel® Server Board S5400SF TPS Server Board Layout Figure 1. Server Board Layout 4 Revision 2.
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Intel® Server Board S5400SF TPS 2.3 Product Overview Connector and Component Locations The following figure shows the board layout of the server board. Each connector and major component is identified by a letter, and a description is given below the figure. A B C D E F G OO NN MM LL KK JJ II HH GG FF EE DD H I CC BB AA Z Y J X K W L V U TR P N M SQ O AF002390 Figure 2. Components and Connector Location Diagram Revision 2.
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Product Overview Intel® Server Board S5400SF TPS Table 1.
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Intel® Server Board S5400SF TPS 2.4 Product Overview Intel® Light-Guided Diagnostics LED Locations B C A D G E F AF002160 A Description Post Code Diagnostic LEDs E Description Processor 2 Fault LED B System ID LED F Processor 1 Fault LED C Status LED G 5 V Standby LED D DIMM Fault LEDs Figure 3. Intel Light-Guided Diagnostics LED Location Diagram Revision 2.
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Product Overview 2.5 Intel® Server Board S5400SF TPS External I/O Connector Locations The drawing below shows the layout of the rear I/O components for the server board. A G B C D E F H AF002161 A B C D PS/2 Mouse PS/2 Keyboard Serial Port B NIC port 1 (1 Gb) E F G H NIC port 2 (1 Gb) Video USB port 5 USB port 6 Figure 4. Intel® Server Board S5400SF External I/O Layout 8 Revision 2.
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Intel® Server Board S5400SF TPS 3. Functional Architecture Functional Architecture The architecture and design of the Intel® Server Board S5400SF is based on the Intel® 5400 Chipset. The chipset is designed for systems using the Intel® Xeon® processor 5000 sequence with front-side bus speeds of 1066 MHz, 1333 MHz, or 1600 MHz.
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Functional Architecture Intel® Server Board S5400SF TPS Processors VRD11/ CPU 0 CPU 0 VRD11/ CPU 1 CPU 1 667/800 MHz FSB0 FSB1 CH 0 Memory FBD Channel A Branch 0 Riser Card Slot Ports PCIe* GEN2 x16 5, 6, 7, 8 (16 GB/s) Intel® 5400 Memory Controller Hub CH 1 CH 2 FBD Channel B FBD Channel C Branch 1 (MCH) Port 9 Port 0 Port 4 ESI CH 3 FBD Channel D DIMM A2 DIMM A3 DIMM A4 DIMM B1 DIMM B2 DIMM B3 DIMM B4 DIMM C1 DIMM C2 DIMM C3 DIMM C4 DIMM D1 DIMM D2 DIMM D3 DIMM D4 L
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Intel® Server Board S5400SF TPS Functional Architecture Table 2. Processor Support Matrix for a list of supported processors. Note: Only Intel® Xeon® processors listed in Revision 2.
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Functional Architecture Intel® Server Board S5400SF TPS Table 2 are supported on this server board. Support for Intel® Xeon® processor 5100 series and 5300 series is limited to Low Voltage SKUs only on this server platform. 12 Revision 2.
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Intel® Server Board S5400SF TPS Functional Architecture Table 2. Processor Support Matrix Processor Family ® ® ® ® Intel Xeon processor 5138 Core Count 2 System Bus Speed 1066 MHz Core Frequency 2.13 GHz Cache Watts 4 MB shared 35 Intel Xeon processor 5148 2 1333 MHz 2.33 GHz 4 MB shared 40 Intel® Xeon® processor L5310 4 1066 MHz 1.60 GHz 8 MB shared 50 Intel® Xeon® processor L5320 4 1066 MHz 1.86 GHz 8 MB shared 50 Intel® Xeon® processor L5335 4 1333 MHz 2.
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Functional Architecture Intel® Server Board S5400SF TPS Table 3. Mixed Processor Configurations Error Processor family not Identical Severity Fatal System Action The BIOS detects the error condition and responds as follows: Logs the error into the system event log (SEL) Alerts the Integrated BMC of the configuration error with an IPMI command.
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Intel® Server Board S5400SF TPS 3.1.2 Functional Architecture Multiple Processor Initialization IA-32 processors have a microcode-based bootstrap processor (BSP) arbitration protocol. The BSP starts executing from the reset vector (F000:FFF0h). A processor that does not perform the role of BSP is referred to as an application processor (AP).
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Functional Architecture Intel® Server Board S5400SF TPS Intel® EM64T operating modes are not manually selectable. The system BIOS, hardware drivers, operating system, and applications that are in use determine the operating mode in use.
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Intel® Server Board S5400SF TPS Functional Architecture Note: If the setup option is changed to enable or disable the Intel® Virtualization Technology setting in the processor, the user must perform an AC power cycle for the change to take effect. 3.1.8 Platform Environmental Control Interface (PECI) PECI is a thermal management interface that uses a single wire bus interface to provide a communication channel between an Intel® processor and an external monitoring device (PECI host controller).
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Functional Architecture Intel® Server Board S5400SF TPS Heatsink assembly Thermal Interface Material (TIM) Server Board TP02091 CEK Spring Chassis AF002163 Figure 6. CEK Processor Mounting 3.2 Intel® 5400 Memory Controller Hub Chipset (Intel® 5400 MCH Chipset) This section describes the general functionality of the memory controller hub as it is implemented on the Intel® Server Board S5400SF.
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Intel® Server Board S5400SF TPS 3.2.1 Functional Architecture Processor Front-Side Buses The MCH supports two independent point-to-point processor front-side bus (FSB) interfaces. Each front-side bus is 64 bits wide. Depending on the installed processor, the interfaces operate using a 266 MHz,333 MHz, or 400 MHz clock, which is then quad pumped to support 1066 MT/s, 1333 MT/s, and 1600 MT/s transfer rates respectively.
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Functional Architecture Intel® Server Board S5400SF TPS The Snoop Filter lookup latency is four SF-clocks or two MCH core clocks to support single snoop stall in an idle condition (single request issued from either bus). If both buses make requests simultaneously, the snoop-filter always selects bus 0 first. In such a scenario, bus 0 request has one snoop-stall and bus 1 request has two snoop-stalls.
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Intel® Server Board S5400SF TPS Functional Architecture Note: The use of 800 MHz FBDIMMs is only supported with Intel® Xeon® processors that support a 1600 MHz front-side bus. Using these FBDIMMs with processors that support slower front-side bus frequencies is not supported on this server board. On the Intel® Server Board S5400SF, a pair of channels becomes a branch where Branch 0 consists of channels A and B, and Branch 1 consists of channels C and D.
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Functional Architecture Intel® Server Board S5400SF TPS The following table lists the currently supported memory types: Table 7.
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Intel® Server Board S5400SF TPS 3.2.3.2 Functional Architecture DIMM Population Rules and Supported DIMM Configurations Intel supported DIMM population configurations for this server board are shown in the following table: Supported and Validated configuration : Slot is populated Supported but not validated configuration : Slot is populated Slot is not populated Table 8.
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Functional Architecture Intel® Server Board S5400SF TPS The DIMM population rules for this server board are as follows: 3.2.3.3 Within a branch, DIMMs must be populated in slot order starting with Slot 1 for each channel, followed by slot 2, then slot 3 and ending with slot 4. DIMMs must be populated in matching pairs across channels within a given branch.
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Intel® Server Board S5400SF TPS 3.2.3.4 Functional Architecture Memory upgrades The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must cover the same slot position on both channels. DIMMs pairs must be identical with respect to size, speed, and organization. DIMMs that cover adjacent slot positions do not need to be identical.
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Functional Architecture Intel® Server Board S5400SF TPS When the branch operates in the single-channel mode, the MCH supports an 8-byte-over-32byte Single Error Correct, Double Error Detect (SECDED+) code. It is the same ECC code that is used in the dual-channel mode, but the number of devices over which the codeword is defined is half, thereby reducing the SDDC properties to SECDED+.
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Intel® Server Board S5400SF TPS 3.2.3.7 Functional Architecture FBD Memory Thermal Management ® The Intel 5400 MCH Chipset implements an adaptive throttling methodology to limit the number of memory requests to the FBDIMMs. This methodology is comprised of the following: Activation throttling: Consists of closed/open loop throttling of activates on the FBDIMM. - Closed Loop Thermal Activate Throttle Control when the temperature of the FBDIMMs increases beyond a specified threshold.
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Functional Architecture Intel® Server Board S5400SF TPS system, the BIOS halts with a POST Diagnostic LED code 0xE1 (no memory detected) and halts the system. Any of the above errors causes a memory error beep code. 3.2.3.8.3 Publishing System Memory The BIOS displays the “Total Memory” of the system during POST if Display Logo is disabled in the BIOS setup.
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Intel® Server Board S5400SF TPS 3.2.3.8.4 Functional Architecture Memory Interleaving In general, to optimize memory accesses, the BIOS enables Branch Interleaving, which allows the chipset to interleave data for successive cache-lines between the autonomous branches. Additionally, the Intel® 5400 MCH Chipset also provides interleaving across logical memory devices called ranks. A pair of single-ranked lock-stepped FBDIMMs constitutes a memory rank.
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Functional Architecture Intel® Server Board S5400SF TPS During POST, the BIOS captures and reports memory BIST errors. At runtime, the BIOS captures and reports correctable, uncorrectable, and fatal errors occurring in the memory subsystem. 3.2.3.9.1 Faulty FBDIMMs The BIOS provides detection of a faulty or failing FBDIMM. A FBDIMM is considered faulty if it fails the memory BIST. The BIOS enables the in-built memory BIST engine in the Intel® 5400 MCH Chipset during memory initialization in POST.
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Intel® Server Board S5400SF TPS Functional Architecture The BIOS initializes the correctable error leaky bucket counters to a value of ten for correctable ECC errors. These counters are on a per-rank basis. A rank applies to a pair of FBDIMMs on adjacent channels functioning in lock-stepped mode. 3.2.3.9.3.1 BIOS Policies on Correctable Errors For each correctable error that occurs before the threshold is reached, the BIOS logs a “Correctable Error” SEL entry.
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Functional Architecture Intel® Server Board S5400SF TPS 3.2.3.9.5.1 BIOS Policies on Uncorrectable Errors For uncorrectable errors, the BIOS logs a single “Uncorrectable Error” SEL entry. The BIOS then generates an NMI. 3.2.3.10 Memory Error Reporting Memory errors are reported through a variety of platform-specific elements, as described in the following table. Table 9.
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Intel® Server Board S5400SF TPS 3.2.3.10.2 Functional Architecture DIMM Fault Indicator LEDs Intel® server boards have a fault-indicator LED next to each DIMM socket. The LEDs are turned on when the FBDIMM on the adjacent DIMM socket is determined to be faulty. The generic usage model for the DIMM Fault LEDs is as follows: Table 11. DIMM Fault LED Behavior Summary Error Event A FBDIMM fails Memory BIST during POST. N/A Mode of Operation Description DIMM LED for the failing FBDIMM is turned on.
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Functional Architecture Intel® Server Board S5400SF TPS LPC bus interface PC-compatible timer/counter and DMA controllers APIC and 8259 interrupt controller Power management System RTC General purpose I/O This section describes the functionality of most of the listed features as they pertain to this server board. For more detail information, see the Intel® Enterprise South Bridge 2 External Design Specification. 3.3.
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Intel® Server Board S5400SF TPS Functional Architecture At least two SATA hard disk drives attached to on-board SATA connectors Intel® Embedded Server RAID Technology II is not available in the following configurations: When the SATA controller is in compatible mode When the Intel® Embedded Server RAID Technology II has been disabled. 3.3.1.
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Functional Architecture Intel® Server Board S5400SF TPS Expansion bus allowing connection to an external Flash PROM (asynchronous or synchronous), SRAM, or SDRAM.
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Intel® Server Board S5400SF TPS 3.3.4.2 Functional Architecture Legacy USB Support The BIOS supports PS/2 emulation of USB keyboards and mice. During POST, the BIOS initializes and configures the root hub ports and then searches for a keyboard and/or a mouse on the USB hub and then enables them. 3.3.5 System Management Bus (SMBus 2.0) ® The Intel 6321ESB I/O Controller Hub contains a SMBus host interface that allows the processor to communicate with SMBus slaves.
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Functional Architecture Intel® Server Board S5400SF TPS PCI Express* Gen 2 bit lane is 5 Gbit/s similarly with a maximum theoretical realized bandwidth of 2 GB/s in each direction. The Gen 2 speeds are only supported for the x16 high-performance PCI Express* interfaces. Each of the MCH PCI Express* ports are organized as four bidirectional bit lanes, and are referred to as a x4 port. The following table lists the characteristics of each PCI bus segment used on this server board: Table 12.
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Intel® Server Board S5400SF TPS 3.4.4 Functional Architecture MCH to Intel® 6321ESB I/O Controller Hub Chip-to-Chip Interface: Two x4 PCI Express* Bus Segments The Enterprise Southbridge Interface (ESI) in the MCH is the chip-to-chip connection to the Intel® 6321ESB I/O Controller Hub. The ESI is a specialized inter-chip interface based upon the PCI Express* Base Specification, Revision 1.1 with special commands/features added to enhance the PCI Express* interface for enterprise applications.
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Functional Architecture Intel® Server Board S5400SF TPS In the legacy mode, the BIOS supports the INT 1Ah PCI BIOS interface calls. 3.4.8 Automatic IRQ Assignment The BIOS automatically assigns IRQs to devices in the system for legacy compatibility. No method is provided to manually configure the IRQs for devices. 3.4.
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Intel® Server Board S5400SF TPS 3.5.1 Functional Architecture Video Modes The ATI* ES1000 chip supports all standard IBM* VGA modes. The following table shows the 2D modes supported for both CRT and LCD. Table 13.
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Functional Architecture 3.6 Intel® Server Board S5400SF TPS Network Interface Controller (NIC) Network interface support is provided from the built-in dual GbE MAC features of the Intel® 6321ESB I/O Controller Hub in conjunction with the Intel® 82563EB compact Physical Layer Transceiver (PHY). Together, they provide the server board with support for dual LAN ports designed for 10/100/1000 Mbps operation.
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Intel® Server Board S5400SF TPS Functional Architecture Two additional MAC addresses are assigned to the Integrated Baseboard Management Controller (Integrated BMC) embedded in the Intel® 6321ESB I/O Controller Hub. These MAC addresses are used by the Integrated BMC’s embedded network stack to enable IPMI remote management over LAN. Integrated BMC LAN Channel 1 is assigned the NIC1 MAC address + 2, and Integrated BMC LAN Channel 2 is assigned the NIC1 MAC address + 3. 3.
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Functional Architecture Intel® Server Board S5400SF TPS DSR signal (Default), the jumper block must be configured with the serial port jumper over pins 3 and 4. Pin 1 on the jumper is identified by “*”. Note: By default, the rear RJ-45 serial port is configured to support a DSR signal. This configuration is compatible with the Cisco standard. J9D1 1-2: DCD to DTR 3-4: DSR to DTR (factory default) AF002168 Figure 10.
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Intel® Server Board S5400SF TPS 3.7.2 Functional Architecture Floppy Disk Controller The server board does not support a floppy disk controller (FDC) interface. However, the system BIOS does recognize USB floppy devices. 3.7.3 Keyboard and Mouse Support Dual stacked PS/2 ports, located on the back edge of the server board, are provided for keyboard and mouse support. Either port can support a mouse or keyboard. Neither port supports hot plugging.
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Server Management 4. Intel® Server Board S5400SF TPS Server Management The server management subsystem is a major component embedded into the design of the server board. It is comprised of several communication buses, system BIOS, the Integrated Baseboard Management Controller (Integrated BMC) features of the Intel® 6321ESB I/O Controller Hub, multiple voltage and thermal sensors, and Integrated BMC Firmware.
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Intel® Server Board S5400SF TPS Server Management Figure 11. SMBus Block Diagram 4.1 Intel® 6321ESB I/O Controller Hub Integrated Baseboard Management Controller (Integrated BMC) Feature Set This server board supports the following Integrated Baseboard Management Controller features of the Intel® 6321ESB I/O Controller Hub. 4.1.1 IPMI 2.
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Server Management Intel® Server Board S5400SF TPS Platform event filtering (PEF) device functionality Event receiver device functionality: The Integrated BMC receives and processes events from other system subsystems. Field replaceable unit (FRU) inventory device functionality: The Integrated BMC supports access to system FRU devices using IPMI FRU commands. System event log (SEL) device functionality: The Integrated BMC supports and provides access to a SEL.
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Intel® Server Board S5400SF TPS Server Management Beep code generation: The Integrated BMC generates diagnostic beep codes for fault conditions. Hot-swap backplane support: The Integrated BMC pushes the power supply state to the hot-swap controller. System GUID storage and retrieval. Memory RAS: The Integrated BMC provides sensors to track the DIMM state and memory RAS redundancy state.
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Server Management - 4.2 Intel® Server Board S5400SF TPS Integrated BMC notification to Intel® RMM2 of select Integrated BMC status changes. Advanced Configuration and Power Interface (ACPI) The Integrated BMC features work with the ACPI BIOS and with the hardware features of the server board. The following sub-sections illustrate these capabilities. The following table shows the ACPI power states. Table 18. ACPI Power States State S0 Supported Yes S1 Yes Sleeping. Hardware context maintained.
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Intel® Server Board S5400SF TPS Server Management The power, sleep, reset, front panel NMI, and ID buttons are unprotected. The Integrated BMC detects that the system has exited the ACPI S1 sleep state when it is notified by the BIOS SMI handler. 4.2.5 ACPI S4 Support The following events occur when the ACPI S4 state is entered: The fans are stopped. The normal operating system boot process is not followed while exiting from hibernated state.
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Server Management 4.3.2.1 Intel® Server Board S5400SF TPS Watchdog Timer Timeout Reason Bits To implement FRB2, during POST the BIOS determines whether a Integrated BMC watchdog timer timeout occurred on the previous boot attempt. If it finds that a watchdog timeout did occur, it determines whether that timeout was an FRB2 timeout, a system management software (SMS) timeout, or an intentional, timed hard reset.
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Intel® Server Board S5400SF TPS 4.4.1 Server Management Power LED The green power LED is active when system DC power is on. The power LED is controlled by the BIOS. The power LED reflects a combination of the state of system (DC) power and the system ACPI state. The following table shows the states that can be assumed. Table 19. Power LED Indicator States 4.4.
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Server Management Intel® Server Board S5400SF TPS The following table maps the system state to the LED state: Table 20. System Status LED Indicator States Color Green State Solid on Ok System Status Green ~1 Hz blink Degraded Description System ready System degraded: BIOS detected 1. Unable to use all of the installed memory (more than one DIMM installed).1 2. Correctable errors over a threshold of ten and migrating to a spare DIMM (memory sparing).
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Intel® Server Board S5400SF TPS Color Amber State Solid on Server Management System Status Fatal Description Fatal alarm – system has failed or shutdown: BIOS Detected 1. DIMM failure when there is one DIMM present and no good memory is .present1. 1 2. Run-time memory uncorrectable error in a non-redundant mode . 3. CPU configuration error (for instance, processor stepping mismatch). Integrated BMC Detected 1. CPU IERR signal asserted. 2. CPU 1 is missing. 3. CPU THERMTRIP. 4.
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Server Management 4.4.4.1 Intel® Server Board S5400SF TPS Chassis Intrusion Some systems support chassis intrusion detection. On systems that support chassis intrusion detection, the Integrated BMC monitors the state of the Chassis Intrusion signal and makes the status of the signal available via the Get Chassis Status command and the Physical Security sensor state.
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Intel® Server Board S5400SF TPS 4.4.5 Server Management Secure Mode and Front Panel Lock-out Operation The secure mode feature allows the front panel buttons to be protected against unauthorized use or access. The secure mode is enabled and controlled via the Set Secure Mode Options command.
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Server Management 4.5 Intel® Server Board S5400SF TPS Platform Control This server board has embedded platform control that is capable of automatically adjusting system performance and system acoustic levels. Performance Management Acoustic Management Performance Throttling Integrated Control Thermal Monitoring F a n S peed Control Figure 12. Platform Control 4.5.
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Intel® Server Board S5400SF TPS Server Management Memory throttling is a feature of the Intel® 5400 Chipset to prevent FBDIMM memory from overheating. If the performance of the installed FBDIMMs approaches their supported thermal limit for a given platform, the system BIOS initiates memory throttling. This manages memory performance by limiting bandwidth to the DIMMs, therefore capping the power consumption and preventing the DIMMs from overheating.
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Server Management Intel® Server Board S5400SF TPS Figure 13. Memory throtting mechanisms implemented flow through the system BIOS 60 Revision 2.
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Intel® Server Board S5400SF TPS Server Management FBDIMM Inputs (SPD bytes) System Level Inputs BIOS Setup & FRUSDR Power Property System Ambient Heat Spreader Type Memory Throttle Settings Trise + DRAM Type BIOS MRC Fan Flow Velocity AMB Thermal Limit Altitude DRAM Thermal Limit Pitch Figure 14. Memory Throttle Settings Inputs The following sections describe the functionality of each platform control mechanism: 4.5.
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Server Management Intel® Server Board S5400SF TPS Note: CLTT is the Intel preferred platform control mechanism as it provides the best memory bandwidth performance while providing the lowest system fan acoustics. CLTT is supported by default when FBDIMMs are installed with functional AMB thermal sensors. 4.5.
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Intel® Server Board S5400SF TPS Server Management which specific platform targets are configured, which in turn determines how the system fans operate to meet those targets. Platform profile targets are determined by the type of platform that is selected when running the FRUSDR utility. 4.6 Standard Fan Management The Integrated BMC controls and monitors the system fans. For each fan, there is a fan speed sensor that provides fan failure detection.
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Server Management Intel® Server Board S5400SF TPS Sleep No boost conditions, system in ACPI S1 sleep state, and Integrated BMC configured to transition fan domains to sleep state via the Set ACPI Configuration Mode command. Nominal It is possible to configure a fan domain’s nominal fan speed to be either static (fixed value) or controlled by the state of one or more associated temperature sensors.
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Intel® Server Board S5400SF TPS 4.8.2 Server Management Server Management Software (SMS) Interface The SMS interface is the Integrated BMC host interface. The Integrated BMC implements the SMS KCS interface as described in the IPMI Specification, Version 2.0. 4.8.3 Server Management Mode (SMM) Interface The SMM interface is a KCS interface that is used by the BIOS when interface response time is a concern, such as with the BIOS SMI handler.
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Server Management 4.9 Intel® Server Board S5400SF TPS Event Filtering and Alerting The Integrated BMC implements most of the IPMI 2.0 alerting features. The following features are supported: 4.9.1 PEF Alert-over-LAN Platform Event Filtering The Integrated BMC monitors system health and logs failure events into the SEL. Platform event filtering provides a configurable mechanism to allow events to trigger alert actions.
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Intel® Server Board S5400SF TPS Server Management Table 24.
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Server Management Intel® Server Board S5400SF TPS 4.12 Sensor Data Record (SDR) Repository The Integrated BMC implements the logical sensor data record (SDR) repository as specified in the Intelligent Platform Management Interface Specification, Version 2.0. The SDR repository is accessible via all communication transports. This way out-of-band interfaces can access SDR repository information evn while the system is down.
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Intel® Server Board S5400SF TPS Server Management If the condition that caused the original assertion is no longer present at the time the re-arm occurs, then the entire sequence is as follows: 1. 2. 3. 4. Failure condition occurs and Integrated BMC logs an assertion event. Sensor is re-armed. Integrated BMC clears sensor status and generates a de-assertion event. Sensor is put into “Init in progress” state until sensor is polled again or otherwise updated. 5.
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Server Management Intel® Server Board S5400SF TPS event state (sensor offset) has been asserted, it remains asserted until one of the following occurs: A Rearm Sensor Events command is executed for that processor status sensor. A Processor Retest command is executed. The BIOS sends this command to the Integrated BMC as a result of a user choosing the Processor Retest option from the BIOS Setup screen. AC power cycle occurs.
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Intel® Server Board S5400SF TPS 4.16.4 Server Management Internal Error (IERR) Monitoring The Integrated BMC monitors the IERR signal from each processor and maps this to the IERR offset of the associated processor status sensor. 4.16.5 Dynamic Processor Voltage Monitoring Processors used on Intel® server boards and systems that use the Intel® 5400 Chipset support dynamic operating states in which the processor VIDs can change under program control or due to operating conditions.
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Server Management Intel® Server Board S5400SF TPS 1. AC powering down the server. 2. Installing a processor into slot 1. 3. AC powering on the server. 4.17 Intel® Remote Management Module 2 (Intel RMM2) Support The server board includes a high-density 120-pin Intel® RMM2 connector at location J1C2 providing support for the Intel® Remote Management Module 2 (Intel® RMM2) server management card.
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Intel® Server Board S5400SF TPS 5. System BIOS System BIOS The BIOS is implemented as firmware that resides in a 4 MB Intel® 28F320C3B flash ROM part. It provides hardware-specific initialization algorithms and standard PC-compatible basic input/output (I/O) services, and standard Intel® Server Board features. The Flash ROM also contains firmware for the on-board Ethernet and Video devices. These images are supplied by the device manufacturers and are not specified in this document.
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System BIOS Intel® Server Board S5400SF TPS 00 = Minor Revision Number 0003 = Build ID 05122007 = Build date using MMDDYY format 1200 = Build time using HHMM format The Board ID is available in the SMBIOS type 2 structure in which the phase of the BIOS can be determined by the release notes associated with the image. The board ID is also available in the BIOS setup. The BIOS ID is available in the setup and in the SMBIOS type 0 structure. 5.2 5.2.
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Intel® Server Board S5400SF TPS 5.2.2.1 System BIOS Operation The BIOS setup has the following features: Localization: The BIOS setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard. The Intel® server board BIOS is only available in English. Console Redirection: The BIOS setup is functional via console redirection over various terminal emulation standards. This may limit some functionality for compatibility, e.g.
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System BIOS Intel® Server Board S5400SF TPS password, a menu feature’s value may or may not be changed. If a value cannot be changed, its field is made inaccessible and appears grayed out. Table 28. BIOS Setup: Keyboard Command Bar Key Option Execute Command Description The key is used to activate sub-menus when the selected feature is a submenu, or to display a pick list if a selected option has a value field, or to select a sub-field for multi-valued features like time and date.
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Intel® Server Board S5400SF TPS Key Option Save and Exit System BIOS Description Pressing causes the following message to appear: Save configuration and reset? Yes No If “Yes” is highlighted and is pressed, all changes are saved and the Setup is exited. If “No” is highlighted and is pressed, or the key is pressed, the user is returned to where they were before was pressed without affecting any existing values. 5.2.2.
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System BIOS Intel® Server Board S5400SF TPS 5.2.3.1 Main Screen The Main screen is the screen that is first displayed when the BIOS Setup is entered, unless an error has occurred. If an error has occurred, the Error Manager screen is displayed instead. Main Advance d Security Server Management Boot Options Boot Manager Logged in as Platform ID System BIOS Version S5400.86B.xx.yy.
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Intel® Server Board S5400SF TPS System BIOS Table 29. Setup Utility — Main Screen Fields Setup Item Logged in as Options Help Text Platform ID System BIOS Version Information only. Displays the current BIOS version. xx = major version yy = minor version zzzz = build number Information only. Displays the current BIOS build date. Build Date Processor Information only. Displays Intel processor name and the speed of the CPU.
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System BIOS Intel® Server Board S5400SF TPS Setup Item System Time Options [HH:MM:SS] Help Text System Time has configurable fields for Hours, Minutes, and Seconds. Comments Hours are in 24-hour format. Use [Enter] or [Tab] key to select the next field. Use [+] or [-] key to modify the selected field. 5.2.3.2 Advanced Screen The Advanced screen provides an access point to configure several options. On this screen, the user selects the option that is to be configured.
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Intel® Server Board S5400SF TPS System BIOS Table 30. Setup Utility — Advanced Screen Display Fields Setup Item Processor Configuration Options Help Text View/Configure processor information and settings. Memory Configuration View/Configure memory information and settings. ATA Controller Configuration View/Configure ATA Controller information and settings. Mass Storage Controller Configuration View/Configure mass storage controller information and settings.
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System BIOS Intel® Server Board S5400SF TPS Advanced Processor Configuration Core Count Core Frequency System Bus Frequency Enhanced Intel® SpeedStep Tech Core Multi-processing Intel® Virtualization Technology Intel® VT for Directed I/O Enabled/Disabled Enabled/Disabled Enabled/ Disabled Enabled/Disabled Simulated MSI Support Execute Disable Bit Hardware Prefetcher Adjacent cache line prefetch Enabled/Disabled Enabled/Disab
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Intel® Server Board S5400SF TPS Setup Item Core Multi-processing Options Enabled Disabled System BIOS Help Text Core Multi-processing sets the state of logical processor cores in a package. [Disabled] sets only logical processor core 0 as enabled in each processor package. Comments Note: If disabled, Hyper-Threading Technology will also be automatically disabled.
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System BIOS Intel® Server Board S5400SF TPS 5.2.3.2.1.1 Processor # Information Screen The Processor # Information screen provides a place for the user to view information about a specific processor. To access this screen from the Main screen, select Advanced > Processor > Processor # Information, where # is the processor number you want to see.
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Intel® Server Board S5400SF TPS 5.2.3.2.2 System BIOS Memory Screen The Memory screen allows the user to view details about the system memory FBDIMMs that are installed. This screen also allows the user to open the Configure Memory RAS and Performance screen. To access this screen from the Main screen, choose Advanced > Memory. Note: The following screenshot is for reference purposes only. The actual BIOS setup screen accurately reflects the number of DIMM slots found on the server board.
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System BIOS Intel® Server Board S5400SF TPS Table 33. Setup Utility — Memory Configuration Screen Fields Setup Item Total Memory Options Help Text Comments Information only. The amount of memory available in the system in the form of installed FBDIMMs, in units of MB or GB. Effective Memory Information only. The amount of memory effective in MB or GB. The Effective Memory is the difference between Total Physical Memory and the sum of all memory reserved for internal usage, RAS redundancy and SMRAM.
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Intel® Server Board S5400SF TPS System BIOS 5.2.3.2.2.1 Memory RAS and Performance Configuration Screen The Configure Memory RAS and Performance screen provides fields to customize several memory configuration options, such as whether to use Memory Sparing. To access this screen from the Main screen, choose Advanced > Memory > Configure Memory RAS and Performance.
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System BIOS Intel® Server Board S5400SF TPS Setup Item Snoop Filter Options Enabled Disabled Help Text The Snoop Filter component monitors and controls the data transactions between memory and the processor(s). FSB High Bandwidth Optimization Enabled Disabled [Enabled] – Optimize Front-Side Bus for higher bandwidth when 1333 MHz FSB or faster processor(s) are installed. Comments Information only. This option is set to enabled always. Note: Some applications benefit from this option. [Enabled]. 5.
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Intel® Server Board S5400SF TPS System BIOS Table 35. Setup Utility — ATA Controller Configuration Screen Fields Setup Item Onboard PATA Controller Options Enabled Disabled Onboard SATA Controller Enabled SATA Mode Enhanced Disabled Legacy Help Text Onboard Parallel ATA (PATA) controller. Comments Onboard Serial ATA (SATA) controller. When enabled, the SATA controller can be configured in IDE, RAID, or AHCI Mode. RAID and AHCI modes are mutually exclusive.
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System BIOS Setup Item AHCI Mode Intel® Server Board S5400SF TPS Options Help Text Advanced Host Controller Interface (AHCI) option ROM will enumerate all AHCI devices connected to the SATA ports. Enabled Disabled Contact your OS vendor regarding OS support of this feature. Configure SATA as RAID Enabled SATA controller will be in RAID mode and the Intel® RAID for Serial ATA option ROM will execute.
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Intel® Server Board S5400SF TPS 5.2.3.2.4 System BIOS Mass Storage Controller Screen The Mass Storage screen provides fields to configure when a SAS controller is present on the server board, midplane or backplane of an Intel® system. To access this screen from the Main menu, choose Advanced > Mass Storage. Advanced Mass Storage Controller Configuration SAS Controller Enabled/Disabled Configure SAS as SW RAID Enabled/Disabled Figure 23.
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System BIOS Intel® Server Board S5400SF TPS Advanced Serial Port Configuration Serial A Enable Enabled/Disabled Address 3F8h/2F8h/3E8h/2E8h IRQ 3 or 4 Serial B Enable Enabled/Disabled Address 3F8h/2F8h/3E8h/2E8h IRQ 3 or 4 Figure 24. Setup Utility — Serial Port Configuration Screen Display Table 37. Setup Utility — Serial Ports Configuration Screen Fields Setup Item Serial A Enable Options Enabled Disabled Help Text Enable or Disable Serial port A.
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Intel® Server Board S5400SF TPS System BIOS Advanced USB Configuration Detected USB Devices USB Controller Enabled/Disabled Legacy USB Support Enabled/Disabled/Auto Port 60/64 Emulation Enabled/Disabled USB Mass Storage Device Configuration Device Reset timeout 10 sec/20 sec/30 sec/40 sec Storage Emulation Auto/Floppy/Forced FDD/Hard Disk/CD-ROM USB 2.0 controller Enabled/Disabled Figure 25.
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System BIOS Intel® Server Board S5400SF TPS Table 38. Setup Utility — USB Controller Configuration Screen Fields Setup Item Detected USB Devices Options Help Text USB Controller Enabled Disabled [Enabled] - All on-board USB controllers are turned on and made accessible by the OS. [Disabled] - All on-board USB controllers are turned off and made inaccessible by the OS. Legacy USB Support Enabled Disabled Auto PS/2 emulation for USB keyboard and USB mouse devices.
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Intel® Server Board S5400SF TPS System BIOS Advanced PCI Configuration Memory Mapped I/O Start Address 1.50GB/1.75GB/2.00GB/2.25GB/2.5GB/2.75GB/3.0GB /3.25GB/3.5GB Memory Mapped I/O above 4GB Enabled/Disabled Onboard Video Enabled/Disabled Dual Monitor Video Enabled/Disabled Onboard NIC1 ROM Enabled/Disabled Onboard NIC2 ROM Enabled/Disabled I/O Module NIC ROM Enabled/Disabled NIC 1 MAC Address NIC 2 MAC Address Intel® I/OAT Enabled/Disabled Figure 26.
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System BIOS Intel® Server Board S5400SF TPS Setup Item Onboard Video Dual Monitor Video Onboard NIC ROM Options Enabled Disabled Help Text On-board video controller. Enabled Disabled Both the on-board video controller and an add-in video adapter are enabled for system video. The on-board video controller is the primary video device. Enabled Disabled Load the embedded option ROM for the on-board network controllers.
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Intel® Server Board S5400SF TPS System BIOS Table 40. Setup Utility — System Acoustic and Performance Configuration Screeen Fields Setup Item Throttling Mode Options Closed Loop Open Loop Help Text Open Loop does not rely on a thermal sensor on the board and sets up a static level which equates in a fixed bandwidth. Closed Loop will allow the system to achieve higher performance by monitoring system temps and adjusting bandwidth. Comments When CLTT fails, Throttling Mode defaults to OLTT.
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System BIOS Intel® Server Board S5400SF TPS Table 41. Setup Utility — Security Configuration Screen Fields Setup Item Administrator Password Status Options User Password Status Set Administrator Password [123abcd] Administrator password is used to control change access in the BIOS Setup utility. Only alphanumeric characters can be used. Maximum length is 7 characters. It is case sensitive.
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Intel® Server Board S5400SF TPS Advance d Main System BIOS Security Server Management Boot Options Boot Manager Assert NMI on SERR Enabled/Disabled Assert NMI on PERR Enabled/Disabled Resume on AC Power Loss Stay Off /Last state/ Reset Clear System Event Log Enabled/Disabled Windows Hardware Error Architecture Enabled/Disabled FRB-2 Enable Enabled/Disabled O/S Boot Watchdog Timer Enabled/Disabled O/S Boot Watchdog Timer Policy Power off/Reset O/S Boot Watchdog Timer Timeout 5 minute
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System BIOS Intel® Server Board S5400SF TPS Setup Item FRB-2 Enable Options Enabled Disabled Help Text Fault Resilient Boot (FRB). The BIOS programs the Integrated BMC watchdog timer for approximately 6 minutes. If the BIOS does not complete POST before the timer expires, the Integrated BMC resets the system. O/S Boot Watchdog Timer Enabled The BIOS programs the watchdog timer with the timeout value selected.
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Intel® Server Board S5400SF TPS System BIOS Table 43. Setup Utility — Console Redirection Configuration Fields Setup Item Console Redirection Options Disabled Serial A Serial B Help Text Console redirection allows a serial port to be used for server management tasks. [Disabled] - No console redirection. [Serial Port A] - Configure serial port A for console redirection. [Serial Port B] - Configure serial port B for console redirection.
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System BIOS Intel® Server Board S5400SF TPS Server Management System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number BMC Firmware Revision HSC Firmware Revision SDR Revision UUID Figure 31. Setup Utility — Server Management System Information Screen Display Table 44.
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Intel® Server Board S5400SF TPS Main Advance d Security System BIOS Server Management Boot Options Boot Timeout <0 - 65535> Boot Option #1 Boot Option #2 Boot Option #x Boot Option Retry Enabled/Disabled Boot Manager Hard Disk Order CDROM Order Floppy Order Network Device Order BEV Device Order Figure 32. Setup Utility — Boot Options Screen Display Table 45.
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System BIOS Intel® Server Board S5400SF TPS Setup Item Floppy Order Help Text Set floppy disk boot order by selecting the boot option for this position. Comments Appears when more than one floppy drive is available in the system. Network Device Order Set network device boot order by selecting the boot option for this position. Add-in or on-board network devices with a PXE option ROM are two examples of network boot devices. Appears when more than one of these devices is available in the system.
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Intel® Server Board S5400SF TPS 5.2.3.6.2 System BIOS CDROM Order Screen The CDROM Order screen allows the user to control the CD-ROM devices. To access this screen from the Main screen, choose Boot Options > CDROM Order. Boot Options CDROM #1 CDROM #2 Figure 34. Setup Utility — CDROM Order Screen Display Table 47.
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System BIOS Intel® Server Board S5400SF TPS Table 48. Setup Utility — Floppy Order Fields Setup Item Floppy Disk #1 Options Available floppy disk Help Text Set floppy disk boot order by selecting the boot option for this position. Floppy Disk #2 Available floppy disk Set floppy disk boot order by selecting the boot option for this position. 5.2.3.6.4 Comments Network Device Order Screen The Network Device Order screen allows the user to control the network bootable devices.
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Intel® Server Board S5400SF TPS System BIOS Boot Options BEV Device #1 BEV Device #2 Figure 37. Setup Utility — BEV Device Order Screen Display Table 50. Setup Utility — BEV Device Order Fields Setup Item BEV Device #1 Options Available BEV devices Help Text Set the Bootstrap Entry Vector (BEV) device boot order by selecting the boot option for this position. BEV devices require their own proprietary method to load an OS using a bootable option ROM.
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System BIOS Intel® Server Board S5400SF TPS Table 51. Setup Utility — Boot Manager Screen Fields Setup Item Launch EFI Shell Options Help Text Select this option to boot now. Note: This list is not the system boot option order. Use the Boot Options menu to view and configure the system boot option order. Boot Device #x 5.2.3.8 Comments Select this option to boot now. Note: This list is not the system boot option order. Use the Boot Options menu to view and configure the system boot option order.
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Intel® Server Board S5400SF TPS Error Manager System BIOS Exit Save Changes and Exit Discard Changes and Exit Save Changes Discard Changes Load Default Values Save as User Default Values Load User Default Values Figure 40. Setup Utility — Exit Screen Display Table 53. Setup Utility — Exit Screen Fields Setup Item Save Changes and Exit Help Text Exit BIOS Setup utility after saving changes. The system reboots if required. The [F10] key can also be used.
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System BIOS 5.3 Intel® Server Board S5400SF TPS Loading BIOS Defaults Different mechanisms exist for resetting the system configuration to the default values. When a request to reset the system configuration is detected, the BIOS loads the default system configuration values during the next POST. The request to reset the system to the defaults can be generated in the following ways: By pressing from within the BIOS Setup utility. By moving the clear system configuration jumper.
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Intel® Server Board S5400SF TPS System BIOS BIOS Select J3H1 1-2: Force Lower Bank 3 2-3: Normal Operation (Default) 3 AF002171 Figure 41. BIOS Select Jumper Position BIOS updates can be made with the BIOS Select jumper in either of the two positions. The behavior of the system in either of these modes is described below. 5.4.1 BIOS Select Jumper in Normal Mode (Jumper pins 2-3 connected) In the normal mode, the new BIOS image is updated onto the secondary partition and is validated.
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System BIOS Intel® Server Board S5400SF TPS 4. The system boots from the old BIOS. 5. If the new BIOS needs to be used, power off the system and move the jumper to cover pins 2 and 3, then power on the system. 6. If the new BIOS is healthy, the system boots with the new BIOS. or If the BIOS is corrupted or incompatible, the system does not roll back to the healthy BIOS. The user should power down the system, move the jumper to cover pins 1 and 2, power up the server to boot to the older BIOS. 5.4.
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Intel® Server Board S5400SF TPS System BIOS the BIOS does not have working code. Under each of these cases, the user finds that the BIOS is no longer functional. The user should first try to clear the CMOS to return to a default configuration. If clearing the CMOS does not correct the issues, the user can perform a recovery by moving the BIOS Select jumper to cover pins 1 and 2 to boot to the previous version of the BIOS. 5.4.3.1 Recovery Flow The steps to perform a BIOS recovery are as follow: 1.
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Connector/Header Locations and Pin-outs Intel® Server Board S5400SF TPS 6. Connector/Header Locations and Pin-outs 6.1 Board Connector Information The following section provides detailed information regarding all connectors, headers and jumpers on the server board. The following table lists all connector types available on the board and the corresponding reference designators printed on the silkscreen. Table 54.
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Intel® Server Board S5400SF TPS Connector System Recovery Setting Jumpers 6.2 Quantity 3 Connector/Header Locations and Pin-outs On-board Silk Screen Reference Designators J1D2, J1D3, J1D4 Connector Type Jumper Pin Count 3 Power Connectors The main power supply connection is obtained using an SSI-compliant 2x12 pin connector (J3K4). In addition, there are two additional power related connectors: One SSI-compliant 2x4 pin power connector (J3K5) providing support for additional 12 V.
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Connector/Header Locations and Pin-outs Intel® Server Board S5400SF TPS Table 57. Power Supply Signal Connector Pin-out (J1K1) 6.3 6.3.1 Pin 1 Signal SMB_CLK_ESB_FP_PWR_R Color Orange 2 SMB_DAT_ESB_FP_PWR_R Black 3 SMB_ALRT_3_ESB_R Red 4 3.3V SENSE- Yellow 5 3.
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Intel® Server Board S5400SF TPS Connector/Header Locations and Pin-outs Pin 47 Signal Name SPB_IMM_CTS_N Pin 48 Signal Name FM_IMM_PRESENT_N 49 SPB_IMM_DCD_N 50 SPB_IMM_DTR_N 51 SPB_RI_N 52 SPB_IMM_SIN 53 SPB_IMM_SOUT 54 P3V3_AUX 55 P3V3_AUX 56 V_LCDDATA7 57 V_LCDCNTL3 56 V_LCDDATA6 59 P3V3_AUX 60 V_LCDDATA5 61 Reserved - NC 62 V_LCDDATA4 63 Reserved - NC 64 V_LCDDATA3 65 GND 66 V_LCDCNTL1 67 V_LCDCNTL0 68 GND 69 Reserved - NC 70 V_LCDDATA15 71 GND 72 V_L
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Connector/Header Locations and Pin-outs 6.3.2 Intel® Server Board S5400SF TPS Intel® RMM2 NIC Connector (J1B2) The server board provides an internal 30-pin mezzanine style connector (J1B2) to accommodate a proprietary form factor Intel® RMM2 NIC module. The following table details the pin-out of the Intel® RMM2 NIC module connector. Table 59. 30-pin Intel® RMM2 NIC Module Connector Pin-out (J1B2) Pin Signal Name FM_MAN_LAN_TYPE2 1 6.3.
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Intel® Server Board S5400SF TPS 6.4 Connector/Header Locations and Pin-outs Riser Card Slot The server board has one riser card slot capable of supporting PCI Express* x16 Gen 2 riser card. The following table shows the pin-out for this riser slot. Table 62.
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Connector/Header Locations and Pin-outs Pin-Side B 120 Intel® Server Board S5400SF TPS 45 PCI Spec Signal HSOP7 Pin-Side A 45 GND PCI Spec Signal 44 GND 44 HSIN6 43 GND 43 HSIP6 42 HSON6 42 GND 41 HSOP6 41 GND 40 GND 40 HSIN5 39 GND 39 HSIP5 38 HSON5 38 GND 37 HSOP5 37 GND 36 GND 36 HSIN4 35 GND 35 HSIP4 34 HSON4 34 GND 33 HSOP4 33 RSVD 32 GND 32 RSVD 31 PRSNT2# 31 GND 30 RSVD 30 HSIN3 29 GND 29 HSIP3 28 HSON3 28 GND 27 HSOP3 27
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Intel® Server Board S5400SF TPS Pin-Side B 6.5 Connector/Header Locations and Pin-outs PCI Spec Signal Pin-Side A PCI Spec Signal 3 RSVD 3 12V 2 12V 2 12V 1 12V 1 PRSNT1# SSI Control Panel Connector (J3H2) The server board provides a 24-pin SSI control panel connector (J3H2) for use with non-Intel chassis. The following table provides the pin-out for this connector. Table 63.
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Connector/Header Locations and Pin-outs Intel® Server Board S5400SF TPS Power Button — On to Off (operating system absent) The System Control Interrupt (SCI) is masked. The BIOS sets up the power button event to generate an SMI and checks the power button status bit in the ACPI hardware registers when an SMI occurs. If the status bit is set, the BIOS sets the ACPI power state of the machine in the chipset to the OFF state.
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Intel® Server Board S5400SF TPS 6.5.6 Connector/Header Locations and Pin-outs System Status LED Note: The system status LED state shows the state for the current, most severe fault. For example, if there was a critical fault due to one source and a non-critical fault due to another source, the system status LED state would be solid on (the state for the critical fault). The system status LED is a bicolor LED. Green (status) is used to show a normal operation state or a degraded operation.
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Connector/Header Locations and Pin-outs Color Amber State ~1 Hz blink Intel® Server Board S5400SF TPS System Status Non-Fatal Description Non-fatal alarm – system is likely to fail: BIOS Detected 1. In a non-sparing and non-mirroring mode if the threshold of ten correctable errors is crossed within the window1. 2. PCI Express* uncorrectable link errors. Integrated BMC Detected 1. Critical threshold crossed – Voltage, temperature, power nozzle, power gauge, and PROCHOT (Therm Ctrl) sensors. 2.
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Intel® Server Board S5400SF TPS Connector/Header Locations and Pin-outs There is no precedence or lock-out mechanism for the control sources. When a new request arrives, all previous requests are terminated. For example, if the chassis ID LED is blinking and the chassis ID button is pressed, then the chassis ID LED changes to solid on. If the button is pressed again with no intervening commands, the chassis ID LED turns off. 6.
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Connector/Header Locations and Pin-outs Pin KEY A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 Intel® Server Board S5400SF TPS Signal Name BMC_RST_BTN_N FP_PWR_BTN_N FP_ID_BTN GND SMB_IPMB_ 5VSB_SDA SMB_IPMB_ 5VSB_CLK GND LED_ HDD_ACTIVITY_N P3V3 FP_PWR_LED_N_R P3V3_STBY FP_ID_LED_R1_N FM_SIO_TEMP_SENSOR LED_FAN3_FAULT LED_FAN2_FAULT LED_FAN1_FAULT FAN_PWM_CPU1 GND FAN_PWM_CPU2 PCI_FAN_TACH9 FAN_TACH7 FAN_TACH5 FAN_TACH3_H7 FAN_TACH1_H7 6.
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Intel® Server Board S5400SF TPS 6.7.2 Connector/Header Locations and Pin-outs NIC Connectors The server board provides two RJ-45 NIC connectors oriented side by side on the back edge of the board (JA8A1, JA8A2). The pin-out for each connector is identical and is defined in the following table. Table 69. RJ-45 10/100/1000 NIC Connector Pin-out (JA8A1, JA8A2) Pin 1 2 3 4 5 6 7 8 9 10 11 (D1) 12 (D2) 13 (D3) 14 15 16 6.7.
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Connector/Header Locations and Pin-outs Pin 29 31 33 35 37 39 41 43 6.7.
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Intel® Server Board S5400SF TPS 6.7.5 Connector/Header Locations and Pin-outs SATA Connectors The server board provides six Serial ATA (SATA) connectors: SATA-0 (J1H1), SATA-1 (J1G2), SATA-2 (J1G1), SATA-3 (J1F2), SATA-4 (J1F1), and SATA-5 (J1E2), for use with an internal SATA backplane. The pin configuration for each connector is identical and is defined in the following table. Table 72.
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Connector/Header Locations and Pin-outs 6.7.7 Intel® Server Board S5400SF TPS Keyboard and Mouse Connector Two stacked PS/2 ports (J9A1) are provided to support both a keyboard and a mouse. Either PS/2 port can support a mouse or keyboard. The following table details the pin-out of the PS/2 connector. Table 75. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 6.7.
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Intel® Server Board S5400SF TPS Connector/Header Locations and Pin-outs Table 77. Internal USB Connector Pin-out (J1J1) Pin 1 2 3 4 5 6 7 8 9 10 6.
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Connector/Header Locations and Pin-outs Intel® Server Board S5400SF TPS Pin Definition LED_FAN4_FAULT FAN_TACH1_H7 FAN_TACH3_H7 FAN_TACH5 FAN_TACH7 PCI_FAN_TACH9 PCI_FAN_TACH10 13 15 17 19 21 23 25 Pin # 14 16 18 20 22 24 26 Pin Definition LED_FAN5_FAULT FAN_TACH2_H7 FAN_TACH4_H7 FAN_TACH6 FAN_TACH8 CONN_PIN24_R FM_SIO_TEMP_SENSOR Note: Intel Corporation server boards support peripheral components and contain a number of high-density VLSI and power delivery components that need adequate airflow to coo
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Intel® Server Board S5400SF TPS 7. Jumper Block Settings Jumper Block Settings The server board has several 2-pin and 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Pin 1 on each jumper block is denoted by an “*” or “▼”. 7.1 Recovery Jumper Blocks Table 80.
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Jumper Block Settings 7.1.1 Intel® Server Board S5400SF TPS System Administrator/User Password Reset Procedure In the event that the System Administrator and/or User password that are set up in the BIOS Setup utility are lost or forgotten, the server board provides a Password Reset Jumper to clear both passwords. The following procedure outlines the usage model. To reset the password, perform the following steps: 1. Power down the server; do not remove AC power. 2.
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Intel® Server Board S5400SF TPS Jumper Block Settings After successful completion of the firmware update process, the firmware update utility may generate an error stating that the Integrated BMC is still in update mode. 5. Power down and remove AC power. 6. Open the server and move the jumper from the “enabled” position (pins 2-3) to the “disabled” position (pins 1-2). 7. Close the server system and reconnect AC power and power up the server.
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Jumper Block Settings Intel® Server Board S5400SF TPS BIOS Select J3H1 1-2: Force Lower Bank 3 2-3: Normal Operation (Default) 3 AF002171 Figure 44. BIOS Select Jumper (J3H1) Pins At system reset 1-2 Force BIOS to bank 0 2-3 System is configured for normal operation (Default) Note: 1. When performing the BIOS update procedure, the BIOS select jumper must be set to its default position (pins 2-3). 136 Revision 2.
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Intel® Server Board S5400SF TPS 7.3 Jumper Block Settings External RJ-45 Serial Port Jumper Block The jumper block J9D1, located directly behind the external RJ-45 serial port, is used to configure either a DSR or a DCD signal to the connector. J8A3 2 3 4 1-2: DCD to DTR 3-4: DSR to DTR (factory default) AF002172 Figure 45. External RJ-45 Serial Port Configuration Jumper Revision 2.
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Intel® Light-Guided Diagnostics 8. Intel® Server Board S5400SF TPS Intel® Light-Guided Diagnostics The server board has several on-board diagnostic LEDs to assist in troubleshooting board-level issues. Functionality of the on-board LEDs is owned by the Integrated BMC and system BIOS. Many of the LEDs are controlled via the SIO. The Integrated BMC and the BIOS use a chipspecific method to avoid contention when accessing the SIO-based LEDs.
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Intel® Server Board S5400SF TPS 8.2 Intel® Light-Guided Diagnostics System ID LED and System Status LED The server board provides LEDs for both System ID and System Status. System ID LED (Blue) Status LED (Green/Amber) AF002174 Figure 47. System ID LED and System Status LED Locations.
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Intel® Light-Guided Diagnostics Color State Intel® Server Board S5400SF TPS Criticality 5. Description apply to non-redundant subsystems. PCI Express* link errors 6. Amber Blink Non-critical Amber Solid on Critical, nonrecoverable 8.2.1 CPU failure/disabled – if there are two processors and one of them fails 7. Fan alarm – Fan failure. Number of operational fans should be more than minimum number needed to cool the system 8.
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Intel® Server Board S5400SF TPS 8.3 Intel® Light-Guided Diagnostics DIMM Fault LEDs The server board provides a memory fault LED for each DIMM slot. The DIMM fault LED is illuminated when the system BIOS disables the specified DIMM after it reaches a specified number of given failures or if specific critical DIMM failures are detected. For details describing DIMM Fault LED operation, see section 3.2.3.10.2. AF002175 Figure 48. DIMM Fault LED Locations 8.
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Intel® Light-Guided Diagnostics 8.5 Intel® Server Board S5400SF TPS Fan Fault LEDs There is a fan fault LED associated with each fan header. The Integrated BMC lights a fan fault LED if the associated fan tach sensor has a lower critical threshold event status asserted. Fan tach sensors are manual re-arm sensors, therefore once the lower critical threshold has been crossed, the LED remains lit until the sensor is re-armed. These sensors are re-armed at system DC power-on and system reset. 8.
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Intel® Server Board S5400SF TPS Power and Environmental Specifications 9. Power and Environmental Specifications 9.1 Intel® Server Board S5400SF Design Specifications Operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the server board. Exposure to absolute maximum rating conditions for extended periods may affect system reliability.
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Power and Environmental Specifications 9.2 Intel® Server Board S5400SF TPS Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel® Server Board S5400SF, including voltage and current specifications, and power supply on/off sequencing characteristics. The following figure shows the power distribution implemented on this server board. Figure 51. Power Distribution Block Diagram 9.2.
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Intel® Server Board S5400SF TPS 9.2.2 Power and Environmental Specifications Power Supply DC Output Requirements This section is for reference purposes only. Its intent is to provide guidance to system architects planning to use the Intel® Server Board S5400SF in a custom chassis for which a power supply is to be determined. The contents of this section specify the power supply requirements Intel used to develop a 600 Watt power supply for its 1U server platform.
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Power and Environmental Specifications 9.2.4 Intel® Server Board S5400SF TPS Grounding The grounds of the power supply output connector pins provide the power return path. The output connector ground pins should be connected to safety ground (power supply enclosure). This grounding is well designed to ensure passing the maximum allowed common mode noise levels. The power supply is provided with a reliable protective earth ground. All secondary circuits are connected to protective earth ground.
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Intel® Server Board S5400SF TPS 9.2.8 Power and Environmental Specifications Dynamic Loading The output voltages remain within limits for the step loading and capacitive loading specified in the following table. The load transient repetition rate is tested between 50 Hz and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The step load may occur anywhere within the minimum load to the maximum load conditions. Table 87.
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Power and Environmental Specifications Intel® Server Board S5400SF TPS 2. The test setup uses an FET probe such as Tektronix* model P6046 or equivalent. 9.2.12 Ripple/Noise The maximum allowed ripple/noise output of the power supply is defined in the following table. This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors. A 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor are placed at the point of measurement. Table 89. Ripple and Noise +3.
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Intel® Server Board S5400SF TPS Power and Environmental Specifications Table 90. Output Voltage Timing Item Tvout_rise Tvout_on Description Output voltage rise time from each main output. All main outputs must be within regulation of each other within this time. All main outputs must leave regulation within this time. Tvout_off Minimum 5.0 Maximum 70 1 50 Units msec msec 700 msec Note: 1. The 5VSB output voltage rise time should be from 1.0 ms to 25.0 ms.
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Power and Environmental Specifications Intel® Server Board S5400SF TPS Table 91. Turn On/Off Timing Item Tsb_on_delay Tac_on_delay Tvout_holdup Tpwok_holdup Tpson_on_delay Tpson_pwok Tpwok_on Tpwok_off Tpwok_low Tsb_vout T5VSB_holdup Description Delay from AC being applied to 5 VSB being within regulation. Delay from AC being applied to all output voltages being within regulation. Duration for which all output voltages stay within regulation after loss of AC. Measured at 60% of maximum load.
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Intel® Server Board S5400SF TPS 9.2.15 Power and Environmental Specifications Residual Voltage Immunity in Standby Mode The power supply is immune to any residual voltage placed on its outputs (typically a leakage voltage through the system from standby output) up to 500 mV. There is no additional heat generated, or stress of any internal components with this voltage applied to any individual output and all outputs simultaneously.
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Regulatory and Certification Information Intel® Server Board S5400SF TPS 10. Regulatory and Certification Information 10.1 Product Regulatory Compliance Intended Application – This product was evaluated as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations.
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Intel® Server Board S5400SF TPS Regulatory and Certification Information (MDDS) must be produced to illustrate compliance. Due verification of random materials is required as a screening/audit to verify suppliers declarations.
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Regulatory and Certification Information Intel® Server Board S5400SF TPS Regulatory Compliance PB Free Marking Region Environmental Requirements China RoHS Marking China China Recycling Package Marking China Marking (Marked on packaging label) Other Recycling Package Marking Environmental Requirements (Marked on packaging label) 10.2 Electromagnetic Compatibility Notices 10.2.1 FCC (USA) This device complies with Part 15 of the FCC Rules.
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Intel® Server Board S5400SF TPS Regulatory and Certification Information Increase the separation between the equipment and the receiver. Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the grantee of this device could void the user’s authority to operate the equipment.
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Regulatory and Certification Information 10.2.5 Intel® Server Board S5400SF TPS Taiwan Declaration of Conformity (BSMI) The BSMI Certification Marking and EMC warning is located on the outside rear area of the product. 10.2.5.1 Korean Compliance (RRL) English translation of the notice above: 1. 2. 3. 4. 5. 156 Type of Equipment (Model Name): On License and Product Certification No.: On RRL certificate.
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Intel® Server Board S5400SF TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-volt standby is still present even though the server board is powered off. Processors must be installed in order. CPU 1 is located near the edge of the server board and must be populated to operate the board.
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Appendix B: POST Code Diagnostic LED Decoder Intel® Server Board S5400SF TPS Appendix B: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the given POST code to the POST Code Diagnostic LEDs found on the back edge of the server board.
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Intel® Server Board S5400SF TPS Appendix B: POST Code Diagnostic LED Decoder Table 93.
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Appendix B: POST Code Diagnostic LED Decoder Intel® Server Board S5400SF TPS 0x79h Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB G R R A Disabling the console controller 0x7Ah G Checkpoint R Description A R Enabling the console controller Keyboard (PS/2 or USB) 0x90h R OFF OFF R Resetting the keyboard 0x91h R OFF OFF A Disabling the keyboard 0x92h R OFF G R Detecting the presence of the keyboard 0x93h R OFF G A Enabling the keyboard 0x94h R G OFF R Clearing
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Intel® Server Board S5400SF TPS Checkpoint 0xDF Appendix B: POST Code Diagnostic LED Decoder Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB A A G A Description Trying boot device selection Pre-EFI Initialization (PEI) Core 0xE0h R R R OFF Started dispatching early initialization modules (PEIM) 0xE2h R R A OFF Initial memory found, configured, and installed correctly 0xE1h R R R G Reserved for initialization module use (PEIM) 0xE3h R R A G Reserved for initialization modul
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Appendix C: POST Error Messages and Handling Intel® Server Board S5400SF TPS Appendix C: POST Error Messages and Handling Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity.
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Intel® Server Board S5400SF TPS Error Code 85FD 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 852A 852B 852C 852D 852E 852F 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 858A 858B 858C 858D 858E 858F 85A0 85A1 85A2 85A3 85A4 85A5 85A6 85A7 85A8 85A9 85AA 85AB 85AC 85AD 85AE 85AF 8601 8602 8603 8604 92A3 92A9 Appendix C: POST Error Messages and Handling Error Message Memory component could not be configured in the selected RAS mode. DIMM_A1 failed Self Test (BIST). DIMM_A2 failed Self Test (BIST).
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Appendix C: POST Error Messages and Handling Intel® Server Board S5400SF TPS POST Error Beep Codes The following table lists POST error beep codes. Prior to system video initialization, the BIOS uses these beep codes to inform users on error conditions. The beep code is followed by a user visible code on POST progress LEDs. Table 95.
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Intel® Server Board S5400SF TPS Appendix D: EFI Shell Commands Appendix D: EFI Shell Commands The embedded EFI Shell must be accessed when running any of the system update utilities or Platform Confidence Test (PCT). The embedded EFI Shell can be accessed by booting the system and entering the BIOS Setup utility (F2) during POST. From the BIOS Setup utility Main menu, tab over to the Boot Manager menu and select EFI Shell. The following is a list of supported EFI Shell commands.
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Appendix D: EFI Shell Commands Command 166 Intel® Server Board S5400SF TPS Batch-only Description exit No Exits the EFI Shell for/endfor getmtc Yes No Executes commands for each item in a set of items Displays the current monotonic counter value goto Yes Makes batch file execution jump to another location guid No Displays all the GUIDs in the EFI environment help No Displays commands list or verbose help of a command hexedit No Edits with hex mode in full screen If/endif Yes Execut
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Intel® Server Board S5400SF TPS Appendix E: Supported Intel® Server Chassis Appendix E: Supported Intel® Server Chassis The Intel® Server Board S5400SF is supported in the following Intel high-density rack mount server chassis: Intel® Server Chassis SR1560. More details can be found by referencing the Intel® Server System SR1560SF Technical Product Specification (TPS). AF002387 Figure 55.
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Appendix F: 1U PCI Express* Gen 2 Riser Card Intel® Server Board S5400SF TPS Appendix F: 1U PCI Express* Gen 2 Riser Card As used in the Intel® Server System SR1560SF, Intel makes a 1U PCI Express* Gen 2 x16 riser card available for this server board. The following mechanical drawing is for reference purposes only. Figure 56. 1U PCI Express* Gen 2 Riser Card Mechanical Drawing 168 Revision 2.
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Intel® Server Board S5400SF TPS Glossary Glossary This appendix contains important terms used in this document. For ease of use, numeric entries are listed first (e.g., “82460GX”) followed by alpha entries (e.g., “AGP 4x”). Acronyms are followed by non-acronyms.
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Glossary Intel® Server Board S5400SF TPS Term ESI Definition Enterprise South Bridge Interface FBD Fully Buffered DIMM FCBGA Flip Chip Ball Grid Array FMB Flexible Mother Board FRB Fault Resilient Booting FRU Field Replaceable Unit FRUSDR Field Replaceable Unit and Sensor Data Record FSB Front-Side Bus GB 1024 MB GPIO General Purpose I/O GTL Gunning Transceiver Logic GUID Globally Unique Identifier HSC Hot-Swap Controller Hz Hertz (1 cycle/second) I2C Inter-Integrated Circuit
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Intel® Server Board S5400SF TPS Glossary Term MRC Memory Reference Code Definition ms milliseconds MTTR Memory Type Range Register Mux Multiplexor NIC Network Interface Controller NMI Non-maskable Interrupt OBF Output Buffer OEM Original Equipment Manufacturer Ohm Unit of electrical resistance OLTT Open Loop Throughput Throttling PAE Physical Address Extension PATA Parallel ATA PCT Platform Confidence Test PECI Platform Environmental Control Interface PEF Platform Event Filte
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Glossary Intel® Server Board S5400SF TPS Term Definition SIO Server Input/Output SMB Server Management BIOS SMBus System Management Bus SMI Server Management Interrupt (SMI is the highest priority nonmaskable interrupt) SMM Server Management Mode SMS Server Management Software SMTP Simple Mail Transfer Protocol SNMP Simple Network Management Protocol SRAM Static Random Access Memory SPD Serial Presence Detect TIM Thermal Interface Material UART Universal Asynchronous Receiver/Tran
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Intel® Server Board S5400SF TPS Reference Documents Reference Documents See the following documents for additional information: Intel® 5400 Series Server Board BIOS External Product Specification Intel® 5400 Series Server Board Integrated Baseboard Management Controller External Product Specification Intel® 5400 Memory Controller Hub External Design Specification Intel® Enterprise South Bridge 2 (ESB2-E) External Design Specification Intel® Remote Management Module 2 Technical Product Spe