System Configuration User Guide

Term Definition
HSC Hot-swap controller
I-cache Instruction cache. Processor-local cache dedicated for memory locations retrieved through
instruction fetch operations.
I2C Inter-integrated circuit bus
IA Intel
®
architecture
IBF Input buffer
ICH I/O controller hub
IERR Internal error
INIT Initialization signal
IPMB Intelligent Platform Management Bus
IPMI Intelligent Platform Management Interface
ITP In-target probe
KCS Keyboard controller style
KT Keyboard text
KVM Keyboard, video, mouse
LAN Local area network
LCD Liquid crystal display
LPC Low pin count
LUN Logical unit number
MAC Media Access Control
MD5 Message Digest 5. A hashing algorithm that provides higher security than MD2.
MIB Modular information block. A descriptive text translation of a PET event, contained in a MIB file for
use by an SNMP agent hen decoding SEL entries.
ms Millisecond
MUX Multiplexer
NIC Network interface card
NMI Non-maskable interrupt
OBF Output buffer
OEM Original equipment manufacturer
OLTT Open-loop thermal throttling (memory throttling mode)
PCI Peripheral Component Interconnect
PECI Platform Environmental Control Interface
PEF Platform event filtering
PET Platform event trap
PIA Platform information area
PLD Programmable logic device
POST Power-on self-test
PROM Programmable read-only memory
Intel® System Configuration Utility – User Guide 11