Technical Product Specification

Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS
Revision 1.7
Intel order number: D41763-008
64
8.4.7 Ripple/Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors. A
10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor are placed at the point of
measurement.
Table 47. Ripple and Noise
+3.3 V +5 V +12 V
1, 2, 3, 4
-12 V +5 VSB
50mVp-p 50mVp-p 120mVp-p 120mVp-p 50mVp-p
Notes:
1. Maximum continuous total output power should not exceed 670 W.
2. Maximum continuous load on the combined 12 V output should not exceed 48 A.
3. Peak load on the combined 12 V output should not exceed 52 A.
4. Peak total DC output power should not exceed 730 W.
8.4.8 Timing Requirements
The following are the timing requirements for the power supply operation. The output voltages
must rise from 10% to within regulation limits (T
vout_rise
) within 5 to 70 ms. 5 VSB is allowed to
rise from 1.0 ms to 25 ms. All outputs must rise monotonically. Each output voltage should
reach regulation within 50 ms (T
vout_on
) of each other when the power suppy is turned on. Each
output voltage should fall out of regulation within 400 msec (T
vout_off
) of each other when the
power suppy is turned off.
The following tables and diagrams show the timing requirements for the power supply being
turned on and off via the AC input with PSON held low, and the PSON signal with the AC input
applied.
Table 48. Output Voltage Timing
Item Description Minimum Maximum Units
T
vout_rise
Output voltage rise time from each main output. 5.0
1
70
1
ms
T
vout_on
All main outputs must be within regulation of each other within this
time.
50 ms
T
vout_off
All main outputs must leave regulation within this time. 400 ms
Note:
1. The 5VSB output voltage rise time is from 1.0 ms to 25 ms.