Server Board Family Datasheet

Intel® S5000 Server Board Family Datasheet System BIOS
Revision 1.3
Intel order number D38960-006
43
successful retry as “Correctable Memory Error” in the SEL regardless of whether the
originating error was a CRC error or an ECC error.
3.3.10.1.5 FBD Fatal Error Threshold
In addition to standard ECC errors, the BIOS monitors FBD protocol errors reported by the
chipset. FBD protocol errors cause degradation of system memory, and hence it is pointless to
tolerate them to any level. The BIOS maintains an internal software counter to handle FBD
errors. The threshold of this software counter is 1.
3.3.10.1.5.1 BIOS Policies on Uncorrectable Errors
For uncorrectable errors, the BIOS will log a single Uncorrectable Error SEL entry. The BIOS
generates an NMI.
3.3.10.1.6 Error Period
The error period, or decay rate, defines the rate at which the leaky bucket counter values are
decremented. The decay period is the time period for the leaky bucket count to decay to 0.
Since the frequency of errors is directly related to the size of the FBDIMMs, the BIOS uses the
information in the following table to define the optimal period:
FBDIMM
Size
Decay Period
(Approximate Duration)
512 MB 9 days
1 GB 9 days
2 GB 9 days
4 GB 7 days
3.3.10.1.7 Retry on Error
The Intel
®
5000 MCH will issue a retry on all failures. In mirroring mode, the read transactions
occur on the primary image only. Write transactions are issued to both images. The behavior of
the chipset on encountering an error depends on the transaction in which the error was first
detected.
 When the chipset encounters an uncorrectable error on Branch X, it issues a retry on
Branch Y. If the retry succeeds, it corrects the data on both branches and proceeds
normally.
 If the retry from the other branch also fails, and if both branches fail on retry, then the
chipset will reset both branches and report a fatal error to the BIOS.