Server Board Family Datasheet

System BIOS Intel® S5000 Server Board Family Datasheet

Revision 1.3

Intel order number D38960-006

participant ranks, and the process is called Rank Interleaving. The BIOS by default enables 4:1

Rank Interleaving, in which 4 ranks participate in a single cache-line access.

3.3.4 Mixed Speed Memory Modules

The BIOS supports memory modules of mixed speed through a combination of user-selected

input frequency and the capability of each memory module (FBDIMM). This section describes

the expected outcome on installation of FBDIMMs of different frequencies in the system, for a

given user-selected frequency.

3.3.4.1 FBDIMM Characteristics

To program a FBDIMM to function correctly for a given frequency, the BIOS queries each

FBDIMM’s Serial-presence Data (SPD) store. The SPD contains the frequency characteristics

of the FBDIMM, which are measured in terms of the following parameters:

 CAS latency (CL)

 Common clock frequency

 Additive latency (AL)

 Buffer read delay (BRD)

The CAS latency and the additive latency are configurable parameters that are detected by the

BIOS by reading the SPD data of the FBDIMMs. The BRD is the average inherent delay that is

caused by the finite time that the AMB consumes in buffering the data read from the DRAMs

before forwarding it on the northbound or southbound path.

3.3.4.2 Host Frequency and Gear Ratio

The host frequency is the speed of the memory interface of the Intel

5000 Series Chipset. This

frequency determines the speed at which the chipset completes a memory transaction. The

gear ratio determines the relative speed between the processor interface and the memory

interface.

The BIOS supports two frequencies: 533 MHz and 667 MHz. The BIOS also provides an auto-

select feature that provides automatic selection and configuration of the host frequency and

gear ratio.

During memory discovery, the BIOS keeps track of the minimum latency requirements of each

installed FBDIMM by recording relevant latency requirements from each FBDIMM’s SPD data.

The BIOS then arrives at a common frequency that matches the requirements of all components

and then configures the memory system, as well as the FBDIMMs, for that common frequency.

3.3.5 Memory Test

3.3.5.1 Integrated Memory BIST Engine

The Intel

5000 MCH incorporates an integrated Memory Built-in Self Test (BIST) engine that is

enabled to provide extensive coverage of memory errors at both the memory cell level, as well

as the data paths emanating from the FBDIMMs.