Technical Product Specification

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Intel® Remote Management Module IntelP®P RMM Board Architecture

3.1 Media Independent Interface (MII)

A Media Independent Interface (MII) connects to the MAC of the dedicated Ethernet NIC of the

Intel

RMM to the Ethernet PHY located on the Intel

RMM NIC. The MII interface from the

Intel

ASMI connector is wired to the MII pins of the Davicom DM9000E Fast Ethernet Controller

(NIC) chip* on the Intel

RMM.

The Davicom NIC* is connected on board to the local bus of the Intel XScale® processor

PXA255. The Davicom NIC* provides the dedicated, Out Of Band (OOB) 10/100 Mb/S Ethernet

capability to the Intel

RMM.

3.2 B 2.0 (high-speed) Interface

A USB 2.0 (high-speed) interface supports the following:

 ual keyboard

 ual mouse

 l

RMM - Virtual Media

 al utilities

The USB interface from the Intel

ASMI connector is wired to the USB pins of the Phillips 1583

USB 2.0 High Speed interface chip*. The Phillips USB chip* is connected on board to the local

bus of the Intel XScale® processor PXA255

3.3 2 Serial Port Connection

O erial port connection of the Intel

ASMI is connected to the Serial port connection

I cale® processor PXA255 on the Intel

RMM. On the baseboard, the Intel

ASMI

c erial port pins are connected to the system universal asynchronous receiver

ART) within the SIO chip. This connection is to enable serial text console

Connections

P nnections on the Intel

ASMI connector are connected to a buffered I

C bus

c e Intel XScale® processor PXA255 on the Intel

RMM. This IPMB interface

c Intel

RMM to the BMC.

n M provides IPMI satellite controller functionality to the BMC. The IPMB of the

RMM provides bi-directional communication at 100 KHz.

Pins

s on the Intel XScale

processor PXA255 are connected to the Intel

ASMI

c anagement LAN type 1 and 2 pins. The GPIO pins are encoded by the

RMM to indicate support for the MII interface.

Virt

Inte

Loc

COM

M 2 s

ntel XS

tor’s s

itter (U

tion.

IPMB

MB co

e of th

ts the

tel

The C

of the

conne

transm

redire

3.4

The I

interfa

conne

The I

Intel

GPIO

PIO pin

tor’s m

3.5

Two G

conne

Intel

Revision 1.0