Server Board Family Datasheet

Intel® S5000 Server Board Family Datasheet System BIOS
Revision 1.3
Intel order number D38960-006
35
The BIOS uses this in-built Memory BIST engine to perform two specific operations:
 ECC fill to set the memory contents to a known state. This provides a bare minimum
error detection capability, and is referred to as the Basic Memory Test algorithm.
 Extensive FBDIMM testing to search for memory errors on both the memory cells and
the data paths. This is referred to as the Comprehensive Memory Test algorithm.
The Memory BIST engine replaces the traditional BIOS-based software memory tests. The
Memory BIST engine is much faster than the traditional memory tests. The BIOS also uses the
Memory BIST to initialize memory at the end of the memory discovery process. The BIOS does
not execute Memory BIST when the system is waking from an S3 sleep mode (S3 Resume) for
systems that support S3.
3.3.6 Memory Scrub Engine
The Intel
®
5000 MCH incorporates a memory scrub engine. When this integrated component is
enabled, it performs periodic checks on the memory cells, and identifies and corrects single-bit
errors. Two types of scrubbing operations are possible:
 Demand scrubbing – executes when an error is encountered during a normal read/write
of data.
 Patrol scrubbing – proactively walks through populated memory space seeking soft
errors.
The BIOS enables both demand scrubbing and patrol scrubbing by default.
Demand scrubbing is not possible when memory mirroring is enabled. Therefore, the BIOS will
disable it automatically if the memory is configured for mirroring.
3.3.7 Memory Map and Population Rules
The nomenclature to be followed for DIMM sockets is as follows.
DIMM Socket Branch Channel
DIMM_A1 0 A
DIMM_A2 0 A
DIMM_B1 0 B
DIMM_B2 0 B
DIMM_C1 1 C
DIMM_C2 1 C
DIMM_D1 1 D
DIMM_D2 1 D
Note: Memory map and population rules may vary by product. See the server or workstation
Technical Product Specification that applies to your product for more detailed information.