Technical Product Specification

Functional Architecture Intel® Server Boards S5000PSL and S5000XSL TPS

Revision 1.7

Intel order number: D41763-008

3. Functional Architecture

The architecture and design of the Intel

Server Boards S5000PSL and S5000XSL are based

on the Intel

S5000P and S5000X chipsets respectively. These chipsets are designed for

systems that use the Intel

Xeon

processor with system bus speeds of 667 MHz, 1066 MHz,

and 1333 MHz.

The chipset contains two main components: the Memory Controller Hub (MCH) for the host

bridge and the I/O controller hub for the I/O subsystem. The chipset uses the Enterprise South

Bridge (ESB2-E) for the I/O controller hub. This chapter provides a high-level description of the

functionality associated with each chipset component and the architectural blocks that make up

the server board.

For more information about the functional architecture blocks, see the Intel

S5000 Server

Board Family Datasheet.