Technical Product Specification

IntelP®P Remote Management Module Environmental/Electrical Specifications Intel® Remote Management Module

The relationship of the clock, data enable, RGB data and horizontal sync are shown below (The

vertical sync is not shown). The clock frequency varies for different resolutions and refresh

rates.

DVO

CLOCK

DATA_ENABLE

15 15 15 1515

ATA

HSYNC

Figure 8. Frequency Relationships

All of these signals are inputs to the DVC FPGA* on the Intel

RMM. Within the FPGA, the



Video is encrypted

n by the Davicom NIC* on the Intel

RMM across the

4.6.1.1 rted Video Resulutions and Refresh Rates

The t rts the Extended Display Identification Data (EDID) standard data format

(version 1.3). The EDID is a VESA standard that contains basic information concerning monitors

and capabilities. The information includes the following:

e size

 Color characteristics

pre-sets

monitor name

ing actions occur:

Video is captured

Video is compressed

Lastly, video is packetized for transmissio

MII interface to the Intel

RMM NIC.

Suppo

In el RMM suppo

 Vendor information

 Maximum imag

 Factory

 Frequency range limits

 Character strings for the

 Serial number

Revision 1.0