Server Board Family Datasheet

System BIOS Intel® S5000 Server Board Family Datasheet
Revision 1.3
Intel order number D38960-006
40
See the server or workstation Technical Product Specification that applies to your product for
more information.
3.3.9.4.1 Minimum FBDIMM Population for Mirroring
Memory mirroring requires the following minimum requirements:
 Branch configuration: Mirroring requires both branches to be active.
 Interleave configuration: Mirroring requires that interleaving at the channel level be
enabled on both branches such that the FBDIMMs on the adjacent channels work in
lock-step.
As a direct consequence of these requirements, the minimum FBDIMM population is DIMM_A1,
DIMM_B1, DIMM_C1, and DIMM_D1. For more information, see section 3.3.7.
In this mode the pair of DIMM A1 and DIMM B1, and the pair of DIMM_C1 and DIMM_D1
operate in lock-step on Branch 0 and Branch 1 respectively, meeting the requirements listed
above. Therefore, the minimum number of FBDIMMs for mirroring is four, arranged as
mentioned above. The BIOS will disable all non-identical FBDIMMs, or pairs of FBDIMMs,
across the branches to achieve symmetry and balance between the branches.
3.3.9.5 Automatic Thermal Throttling
The Intel
®
5000 sequence MCH performs automatic electrical throttling on the FBDIMMs when
there is heavy memory traffic, as in the case of a memory intensive application, which indirectly
results in a rise in temperature of the advanced memory buffers (AMBs) on the FBDIMMs. The
BIOS always enables electrical throttling.
The BIOS will send a command to the BMC telling it which fan profile is set in BIOS Setup
(acoustic or performance) and then it will send an additional command to get the settings for
that profile. The BIOS uses the parameters retrieved from the thermal sensor data records
(SDR) and the altitude setting from BIOS Setup to configure the memory and the chipset for
memory throttling and fan speed control. If the BIOS fails to get the thermal SDRs, then it will
use the memory reference code (MRC) default settings for the thermal values.
3.3.10 Memory Error Handling
This section describes the BIOS and chipset policies used for handling and reporting errors
occurring in the memory sub-system.
3.3.10.1 Memory Error Classification
The BIOS classifies memory errors into the following categories:
 Correctable ECC errors: errors that occur in memory cells and result in corruption of
memory, but are internally corrected by the ECC engine in the chipset.
 Uncorrectable ECC errors: errors that occur in memory cells and result in data
corruption. The chipset’s ECC engine detects these errors, but cannot correct them.
These errors create a loss of data fidelity and are severe errors.