Server Board Family Datasheet

System BIOS Intel® S5000 Server Board Family Datasheet

Revision 1.3

Intel order number D38960-006

3.3 Memory

The Intel

5000 MCH supports fully-buffered DIMM (FBDIMM) technology. The integrated

Memory Controller Hub in the Intel

5000 MCH divides the FBDIMMs on the board into two

autonomous sets called branches. Each branch has two channels. In dual-channel mode,

FBDIMMs on adjacent channels work in lock-step to provide the same cache line data, and a

combined ECC. In the single-channel mode, only Channel 0 is active.

The BIOS is able to configure the memory controller dynamically in accordance with the

available FBDIMM population and the selected RAS (reliability, availability, serviceability) mode

of operation.

3.3.1 Memory Sizing and Configuration

The BIOS supports various memory module sizes and configurations. These combinations of

sizes and configurations are valid only for FBDIMMs approved by Intel. The BIOS reads the

Serial Presence Detect (SPD) SEEPROMs on each installed memory module to determine the

size and timing characteristics of the installed memory modules (FBDIMMs). The memory-sizing

algorithm then determines the cumulative size of each row of FBDIMMs. The BIOS programs

the memory controller in the chipset accordingly, such that the range of memory accessible from

the processor is mapped into the correct FBDIMM or set of FBDIMMs.

3.3.2 POST Error Codes

The range {0xE0, 0xEF} of POST codes is used for memory errors in early POST. In late POST,

this range is used for reporting other system errors.

 If no memory is available, the system will emit POST Diagnostic LED code 0xE1 and

halt the system.

 If the system is unable to communicate with the FBDIMMs, the BIOS will eventually time

out and report POST Diagnostic LED code 0xE4. This is usually indicative of hardware

failure.

 If a FBDIMM or a set of FBDIMMs on the same FBD memory channel (row) fails Memory

Intel

Interconnect built in self test (Intel

IBIST), or Memory Link Training, the BIOS will

emit POST Diagnostic LED code 0xE6. If all of the memory fails IBIST the system will

act as if no memory is available.

Any of the above errors cause a memory error beep code. Memory beep code errors are

described in Section 5.3.2, POST Code Checkpoints.

3.3.3 Publishing System Memory

 The BIOS displays the total memory of the system during POST if the display logo is

disabled in the BIOS Setup utility. Total memory is the total size of memory discovered

by the BIOS during POST, and is the sum of the individual sizes of installed FBDIMMs.

The total memory is also displayed on the main page of the BIOS Setup utility.

 The BIOS displays the effective memory of the system in the BIOS Setup utility.

Effective memory is the total size of all FBDIMMs that are active (not disabled) and not

used as redundant units.