Server Board Family Datasheet

System BIOS Intel® S5000 Server Board Family Datasheet

Revision 1.3

Intel order number D38960-006

The BIOS will create entries in the multi-processor specification tables to describe dual core

processors.

3.2.16 Intel

Virtualization Technology

Intel

Virtualization Technology is designed to support multiple software environments sharing

the same hardware resources. Each software environment may consist of operating system and

applications. The Intel

Virtualization Technology can be enabled or disabled in BIOS Setup.

The default behavior is disabled.

Note: If the Setup options are changed to enable or disable the Intel

Virtualization Technology

setting in the processor, the user must perform an AC power cycle before the changes will take

effect.

3.2.17 Fake MSI Support

In PCI compatible INTx mode, the Intel® 5000 Series Chipsets supports a maximum of four

unique interrupts. If more than four unique interrupts are used by devices behind the Intel®

5000 Series Chipset root ports, it could result in a potential interrupt scaling problem due to

sharing of interrupts. On an Intel® 5000 based platform that supports eight processor cores, the

configuration allows for interrupt distribution to all eight cores. Since the available number of

unique interrupts (4) is less than the number of available cores (8), the platform cannot take

advantage of all the available cores for interrupt distribution. However, the Intel® 5000 Series

Chipsets provides an interrupt scaling feature called Fake MSI to mitigate this problem.

3.2.17.1 Overview of Fake MSI Support

All PCIe devices are required to support MSI (Message Signaled Interrupt). In this scheme, the

device causes an interrupt by writing the value of the MSI data register to the address contained

in the MSI address register. The resulting memory write transaction is translated through chipset

logic into an interrupt transaction for the appropriate target processor core(s). However, the MSI

scheme requires support in the OS which is not widely available in currently shipping operating

systems. The Fake MSI scheme allows PCIe devices running on such legacy operating systems

to use the MSI mechanism to generate INTx compatible interrupts. This is accomplished by

targeting the MSI memory write to an IOxAPIC in the system.

Under the Fake MSI scheme, PCI-Express devices are programmed to enable MSI functionality,

and given a write path directly to the pin assertion register (PAR) of an IOxAPIC already present

in the platform. The targeted IOxAPIC will now generate an APIC interrupt message in response

to a memory write to the PAR, thus providing equivalent functionality to a virtual (edge-

triggered) wire between the PCI-Express endpoint and the IOxAPIC. The Intel® 5000 Series

Chipsets ensure that PCI ordering rules are maintained for the Fake MSI memory write.

All PCI-Express devices are required to support MSI. When Fake MSI is enabled, the PCI-

Express devices generate a memory transaction with an address equal to I/OxAPIC_MEM_BAR

+ 0x20 (PAR) and a 32-bit data equal to the interrupt vector number corresponding to the

device. This information is stored in the device's MSI address and data registers, and would be

initialized by the system firmware (BIOS) prior to booting a non-MSI aware operating system.