Server Board Family Datasheet

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System BIOS Intel® S5000 Server Board Family Datasheet

Revision 1.3

Intel order number D38960-006

45nm 2P Quad-Core Intel

Xeon

Processors*

TBD TBD TBD TBD Yes*

* Only specific product codes of the Intel

S5000 server and workstation board family can

support the 45nm 2P Dual-Core or 45nm 2P Quad-Core Intel® Xeon® Processors. See the

server or workstation Technical Product Specification that applies to your product for more

information on dual-core or quad-core processor support.

*Only Intel® Xeon processors with system bus speeds of 667MHz, 1066MHz or 1333MHz are

supported in the Intel® S5000 server and workstation board family.

3.2.2 Multiple Processor Initialization

IA-32 processors have a microcode-based bootstrap processor (BSP) arbitration protocol. A

processor that does not perform the role of BSP is referred to as an application processor (AP).

The Intel

5000 Series Chipset memory controller hub (MCH) has two processor system buses,

each of which accommodates a single Multi-Core Intel

Xeon

processor 5000 sequence. At

reset, the hardware arbitration chooses one BSP from the available processor cores per system

bus. However, the BIOS power-on self-test (POST) code requires only one processor for

execution. This requires the BIOS to elect a system BSP using registers in the Intel

5000 MCH.

The BIOS cannot guarantee which processor will be the system BSP, only that a system BSP

will be selected. In the remainder of this document, the system BSP is referred to as the BSP.

The BSP is responsible for executing the BIOS POST and preparing the server to boot the

operating system. At boot time, the server is in virtual wire mode and the BSP alone is

programmed to accept local interrupts (INTR driven by programmable interrupt controller (PIC)

and non-maskable interrupt (NMI).

As a part of the boot process, the BSP wakes each AP. When awakened, an AP programs its

memory type range registers (MTRRs) to be identical to those of the BSP. All APs execute a

halt instruction with their local interrupts disabled. If the BSP determines that an AP exists that

is a lower-featured processor or that has a lower value returned by the CPUID function, the BSP

switches to the lowest-featured processor in the server. The system management mode (SMM)

handler expects all processors to respond to a system management interrupt (SMI).

3.2.3 Mixed Processor Steppings

For optimum performance, only identical processors should be installed. Processor stepping

within a common processor family can be mixed as long as it is listed in the processor

specification updates published by Intel Corporation. The BIOS does not check for mixed

processor steppings. See the Intel

Xeon

Processor Specification Update for supported mixed

processor steppings. See also Table 4 .

3.2.4 Mixed Processor Families

Processor families cannot be mixed. If this condition is detected, an error is reported to the

BMC. See Table 4.

3.2.5 Mixed Processor System Bus Speeds

Processors with different system bus speeds cannot be mixed. If this condition is detected, an

error is reported to the BMC. See Table 4 for details.