Technical Product Specification

Intel® Remote Management Module IntelP®P RMM Board Architecture
3.7.1 BMC_FML_0 Interface
BMC_FML_0 provides a high-speed interface between the BMC on the baseboard and the
Intel
®
RMM. Through this interface, the Intel
®
RMM forwards IPMI 2.0 traffic (UDP/IP traffic to
specific RMCP ports) to the BMC.
The forwarded traffic is received from the network on the dedicated NIC. IPMI return traffic is
transmitted by the BMC to the Intel
®
RMM NIC on the FML, as well.
the baseboard BMC. The
Intel
®
RMM acts as an FML slave device to the FML master within the BMC on the baseboard.
As an FML slave, the Intel
®
RMM controls the SINTEX interrupt line. This interrupt is used to
signal the BMC whenever the Intel
®
RMM wishes to initiate an FML data transfer of any kind.
.7.2 C_FML_1
® ®
tel
®
RMM NIC using the FML bus instead of the MII interface. This scheme is referred to as
the FML/TCO management port.
The chip allows support for the DVO video:
Video compression
 Video packetization
3.7.4 Operating System Support
The Intel XScale® processor PXA255 uses a 32 MB SDRAM chip (8 MB X 32 b). This chip
supports running the embedded Linux Operating System* and all other embedded Intel
®
RMM
firmware.
The embedded firmware of the Intel
®
RMM is stored in a 16 MB flash chip from Intel. Both of
these are attached to the local bus of the Intel XScale® processor PXA255.
3.7.1.1 FML Connection
The FML connection with the Intel
®
RMM resembles a LAN channel to
3 NI
NIC_FML_1 is not used by the Intel RMM. However, it is connected from the Intel ASMI
connector to pins on the FPGA. This could be used to connect the Intel
®
RMM to a baseboard
In
3.7.3 8 MB SDRAM Video Frame Buffer Chip
The DVC FPGA on the Intel
®
RMM uses an 8 MB SDRAM video frame buffer chip by Micron*
 Video capture

 Video encryption
 Video transmission
Revision 1.0
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