Technical Product Specification

IntelP®P RMM Board Architecture Intel® Remote Management Module

3.6 15 Bit DVO Video Source

The 15-bit DVO video source comes from the baseboard’s ATI graphics controller*. The DVO

pins are organized as follows:

 Five red

Five green



ASMI connector are wired to the Xilinx XC3S400-4 FT256

FPGA* on the Intel

RMM. With this FPGA chip, the Avocent Dambrackas Video Compression*

) the video stream:

Lastly, the video stream is transmitted to the Davicom NIC* to be sent out over the IP network.

anagement Link (FML) interfaces:

C_FML_0.

) point-to-point interface that utilizes a single master and a

 Five blue

The DVO signals from the Inte

(DVC algorithm completes the following actions to

 Captures

 Compresses

 Packetizes

 Encrypts

3.7 Intel

ASMI Connector

The Intel ASMI connector implements two Fast M

 BMC_FML_0 and

 NIC_FML_1

Both FML interfaces are wired to the FPGA of the Intel

RMM. However, only the Intel

RMM

uses the BM

The FML bus is a high-speed (8 Mb/S

single slave. The BMC is the FML master and the Intel RMM is the FML slave.

Revision 1.0