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Intel Server Board S3420

Technical Product Specification

Intel order numbe

Revision 1.0

August 2009

Enterprise Platforms and Services Division

r E65697-003

Summary of content (136 pages)

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Intel® Server Board S3420GP Technical Product Specification Intel order number E65697-003 Revision 1.
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Revision History IntelP®P Server Board S3420GP TPS Revision History Date Feb. 2009 Revision Number 0.3 Modifications Initial version May 2009 0.5 Update July. 2009 0.9 Update POST error code and diagram Aug. 2009 1.0 Update MTBF Revision 1.
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IntelP®P Server Board S3420GP TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents IntelP®P Server Board S3420GP TPS Table of Contents 1. 2. 3. Introduction .......................................................................................................................... 2 1.1 Chapter Outline........................................................................................................ 2 1.2 Server Board Use Disclaimer .................................................................................. 2 Overview ..................................
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IntelP®P Server Board S3420GP TPS 3.6.5 Keyboard and Mouse Support ............................................................................... 26 3.6.6 Wake-up Control.................................................................................................... 27 3.7 Video Modes.......................................................................................................... 27 3.7.2 Dual Video .......................................................................................
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Table of Contents 6.3.1 Intel® Remote Management Module 3 (Intel® RMM3) Connector .......................... 66 6.3.2 LCP / IPMB Header ............................................................................................... 67 6.3.3 HSBP Header ........................................................................................................ 67 6.3.4 SGPIO Header....................................................................................................... 67 6.
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IntelP®P Server Board S3420GP TPS Table of Contents 9.4.2 Standby Outputs .................................................................................................... 89 9.4.3 Remote Sense ....................................................................................................... 89 9.4.4 Voltage Regulation ................................................................................................ 89 9.4.5 Dynamic Loading ....................................................
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List of Figures IntelP®P Server Board S3420GP TPS List of Figures Figure 1. Intel® Server Board S3420GPLX Picture ....................................................................... 3 Figure 2. Intel® Server Board S3420GP Layout............................................................................ 4 Figure 3. Intel® Server Board S3420GP – Key Connector and LED Indicator IDENTIFICATION. 6 Figure 4. Intel® Server Board S3420GP – Hole and Component Positions ..................................
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IntelP®P Server Board S3420GP TPS List of Figures Figure 33. Setup Utility – Network Device Order Screen Display ............................................... 62 Figure 34. Setup Utility – Boot Manager Screen Display............................................................ 63 Figure 35. Jumper Blocks (J1A2, J1F1, J1F3, J1F2 and J1F5).................................................. 80 Figure 36. Power Distribution Block Diagram ........................................................................
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List of Tables IntelP®P Server Board S3420GP TPS List of Tables Table 1. Intel® Server Board S3420GP Feature Set ..................................................................... 1 Table 2. Major Board Components ............................................................................................... 5 Table 3. Standard Platform DIMM Nomenclature ....................................................................... 18 Table 4. Memory Configuration Table........................................
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IntelP®P Server Board S3420GP TPS List of Tables Table 33. SSI Processor Power Connector Pin-out (J9C1) ........................................................ 66 Table 34. Intel® RMM3 Connector Pin-out (J2C1) ...................................................................... 66 Table 35. LPC / IPMB Header Pin-out (J1H2) ............................................................................ 67 Table 36. HSBP Header Pin-out (J1J1) .................................................................
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List of Tables IntelP®P Server Board S3420GP TPS Table 67. POST Progress Code LED Example ........................................................................ 109 Table 68. Diagnostic LED POST Code Decoder ...................................................................... 109 Table 69. POST Error Messages and Handling........................................................................ 113 Table 70. POST Error Beep Codes ..........................................................................
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IntelP®P Server Board S3420GP TPS List of Tables Revision 1.
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Introduction 1. IntelP®P Server Board S3420GP TPS Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of the Intel® Server Board S3420GP. In addition, you can obtain design-level information for specific subsystems by ordering the External Product Specifications (EPS) or External Design Specifications (EDS) for a given subsystem.
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IntelP®P Server Board S3420GP TPS 2. Overview Overview The Intel® Server Board S3420GP is a monolithic printed circuit board (PCB) with features designed to support entry-level severs. It has three board SKUs: S3420GPLX, S3420GPLC, and S3420GPV. 2.1 Intel® Server Board S3420GP Feature Set Table 1. Intel® Server Board S3420GP Feature Set Feature Processor Description Support for one Xeon® 3400 Series Processor in FC-LGA 1156 socket package. 2.
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Overview Feature Add-in PCI Card, PCI Express* Card IntelP®P Server Board S3420GP TPS Description Intel® Server Board S3420GPLX • Slot1: One 5V PCI 32 bit / 33 MHz connector. Slot2: One PCI Express* Gen1 x4 (x1 throughput) connector. Slot3: One PCI Express* Gen1 x8 (x4 throughput) connector. Slot4: One PCI Express* Gen2 x8 (x4 throughput) connector. Slot5: One PCI Express* Gen2 x8 (x8 throughput) connector. Slot6: One PCI Express* Gen2 x16 (x8 throughput) connector.
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IntelP®P Server Board S3420GP TPS 2.2 Overview Server Board Layout Figure 1. Intel® Server Board S3420GPLX Picture Revision 1.
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Overview IntelP®P Server Board S3420GP TPS 2.2.1 Server Board Connector and Component Layout The following figure shows the board layout of the server board. Each connector and major component is identified by a number or letter, and 2 provides the description. A B C D E F G H J I K L M N DD O CC BB P AA Z W T V S R Q U X AF003290 Y Figure 2. Intel® Server Board S3420GP Layout Revision 1.
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IntelP®P Server Board S3420GP TPS Overview Table 2. Major Board Components Description A B C D E F G H I J K L M N O P Description Slot 1, 32 Mbit/33 MHz PCI Slot 2, PCI Express* Gen1 x1 (x4 connector) (Intel Server Board S3420GPLX only) Intel RMM3 Connector(Intel Server Board S3420GPLX only) Slot 3, PCI Express* Gen1 x4 (PCI Express* Gen2 compliant) Slot 4, PCI Express* Gen2 x4 (x8 connector) (x8 connector)( Intel® Server Board S3420GPLX only) Slot 5.
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Overview 2.2.2 IntelP®P Server Board S3420GP TPS Intel® Server Board S3420GP Mechanical Drawings Figure 3. Intel® Server Board S3420GP – Key Connector and LED Indicator IDENTIFICATION Revision 1.
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IntelP®P Server Board S3420GP TPS Overview Figure 4. Intel® Server Board S3420GP – Hole and Component Positions Revision 1.
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Overview IntelP®P Server Board S3420GP TPS Figure 5. Intel® Server Board S3420GP – Major Connector Pin Location (1 of 2) Revision 1.
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IntelP®P Server Board S3420GP TPS Overview Figure 6. Intel® Server Board S3420GP –Major Connector Pin Location (2 of 2) Revision 1.
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Overview IntelP®P Server Board S3420GP TPS Figure 7. Intel® Server Board S3420GP – Primary Side Keepout Zone Revision 1.
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IntelP®P Server Board S3420GP TPS Overview Figure 8. Intel® Server Board S3420GP – Secondary Side Keepout Zone Revision 1.
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Overview 2.2.3 IntelP®P Server Board S3420GP TPS Server Board Rear I/O Layout The following figure shows the layout of the rear I/O components for the server board. A Serial Port A C NIC Port 1 (1 Gb) and Dual USB Port Connector B Video D NIC port 2 (1 Gb) and Dual USB Port Connector Figure 9. Intel® Server Board S3420GP Rear I/O Layout Revision 1.
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IntelP®P Server Board S3420GP TPS 3. Functional Architecture Functional Architecture The architecture and design of the Intel® Server Board S3420GP is based on the Intel® 3420 Chipset. The chipset is designed for systems based on the Intel® Xeon® processor in the FCLGA 1156 socket package. The chipset contains two main components: Intel® 3420 Chipset PCI Express* switch (Intel® Server Board S3420GPLX only).
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Functional Architecture IntelP®P Server Board S3420GP TPS S3420GPLC Block Diagram (x16 connector) (x8 connector) Slot 6 ATX - 12" x 9.
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IntelP®P Server Board S3420GP TPS Functional Architecture The server board does not support previous generations of the Intel® Xeon® processors. Intel® Turbo Boost Technology 3.1.2 Intel® Turbo Boost Technology is featured on certain processors in the Intel® Xeon® Processor 3400 Series. Intel® Turbo Boost Technology opportunistically and automatically allows the processor to run faster than the marked frequency if the processor is operating below power, temperature, and current limits.
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Functional Architecture IntelP®P Server Board S3420GP TPS frequency can be 1066/1333 MHz. All RDIMMs and UDIMMs include ECC (Error Correction Code) operation. Various speeds and memory technologies are supported. RAS (Reliability, Availability, and Serviceability) is not supported on the Intel® Server Board S3420GP. 3.2.1 Memory Sizing and Configuration ® The Intel Server Board S3420GP supports various memory module sizes and configurations.
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IntelP®P Server Board S3420GP TPS Functional Architecture Memory BIST, the system acts as if no memory is available, beeping and halting with the POST Diagnostic LED code 0xE8 (No Usable Memory) displayed. z z z 0xEA - Channel Training Error: If the memory initialization process is unable to properly perform the DQ/DQS training on a memory channel, the BIOS emits a beep code and displays POST Diagnostic LED code 0xEA momentarily during the beeping.
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Functional Architecture IntelP®P Server Board S3420GP TPS offered by the Intel® S3420 I/O Hub and a variably-sized Memory Mapped I/O region for the PCI Express* functions. 3.2.3.2 High-Memory Reclaim When 4 GB or more of physical memory is installed (physical memory is the memory installed as DDR3 DIMMs), the reserved memory is lost.
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IntelP®P Server Board S3420GP TPS 3.2.5.1 Functional Architecture TableMemory Subsystem Operating Frequency Determination The rules for determining the operating frequency of the memory channels are simple, but not necessarily straightforward. There are several limiting factors, including the number of DIMMs on a channel and organization of the DIMM - that is, either single-rank (SR), dual-rank (DR), or quad-rank (QR): The speed of the processor’s IMC is the maximum speed possible.
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Functional Architecture IntelP®P Server Board S3420GP TPS Channel A A1 RDIMM A2 Channel B A3 B2 B3 X X X X X X X UDIMM B1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X You must observe the following general rules when selecting and configuring memory to obtain the best performance from the system. 1. DDR3 RDIMMs must always be populated using a fill-farthest method. 2. DDR3 UDIMMs must always be populated on DIMM A1/A2/B1/B2. 3.
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IntelP®P Server Board S3420GP TPS 3.3 Functional Architecture Intel® 3420 Chipset PCH The Intel® 3420 Chipset component is the Platform Controller Hub (PCH). The PCH is designed for use with Intel® processor in a UP server platform.
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Functional Architecture IntelP®P Server Board S3420GP TPS When operating with two PCI Express* controllers, each controller can operate at either 2.5 GT/s or 5.0 GT/s. The PCI Express* architecture is specified in three layers: Transaction Layer, Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries. 3.4.
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IntelP®P Server Board S3420GP TPS Functional Architecture The BIOS supports USB 2.0 mode of operation, and as such supports USB 1.1 and USB 2.0 compliant devices and host controllers. During the pre-boot phase, the BIOS automatically supports the hot addition and hot removal of USB devices and a short beep is emitted to indicate such an action. For example, if a USB device is hot plugged, the BIOS detects the device insertion, initializes the device, and makes it available to the user.
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Functional Architecture IntelP®P Server Board S3420GP TPS 12 10-bit ADCs Eight Fan Tachometers Four PWMs Battery-backed Chassis Intrusion I/O Register JTAG Master Six I2C interfaces General-purpose I/O Ports (16 direct, 64 serial) Additionally, the ServerEngines* Pilot II part integrates a super I/O module with the following features: KCS/BT Interface Two 16C550 Serial Ports Serial IRQ Support 12 GPIO Ports (shared with BMC) LPC to SPI Bridge SMI and PME Support The
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IntelP®P Server Board S3420GP TPS Functional Architecture Integrated BMC Block Diagram Interrupt Controller Fan Tach (12) PWM (4) ADC Thermal USB to Host Code Memory USB 1.1 & USB 2.
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Functional Architecture IntelP®P Server Board S3420GP TPS • Give the customer the option to add a dedicated management 100 Mbit LAN interface to the product. • Provide additional flash space, enabling the Advanced Management functions to support WS-MAN and CIMON. Table 5. Optional RMM3 Advanced Management Board Features Feature Description KVM Redirection Remote console access via keyboard, video, and mouse redirection over LAN. USB Media Redirection Remote USB media access over LAN.
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IntelP®P Server Board S3420GP TPS 3.6.6 Functional Architecture Wake-up Control The super I/O contains functionality that allows various events to power on and power off the system. 3.7 Video Support The server board includes a video controller in an on-board Server Engines* Integrated Baseboard Management Controller along with 64 MB of video DDR2 SDRAM. The SVGA subsystem supports a variety of modes, up to 1600 x 1200 resolution in 8 / 16 / 32 bpp modes under 2D.
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Functional Architecture 3.8 IntelP®P Server Board S3420GP TPS Onboard Video Enabled Disabled Onboard video controller. Warning: System video is completely disabled if this option is disabled and an add-in video adapter is not installed. Dual Monitor Video Enabled Disabled If enabled, both the onboard video controller and an add-in video adapter are enabled for system video. The onboard video controller becomes the primary video device.
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IntelP®P Server Board S3420GP TPS Functional Architecture NIC 2 MAC address – Assigned the NIC 1 MAC address +1 Integrated BMC LAN Channel MAC address – Assigned the NIC 1 MAC address +2 Intel® Remote Management Module 3 (Intel® RMM3) MAC address – Assigned the NIC 1 MAC address +3 Each Intel® Server Board S3420GPLC has the following three MAC addresses assigned to it at the Intel factory: NIC 1 MAC address NIC 2 MAC address – Assigned the NIC 1 MAC address +1 Integrated BMC LAN Channel MAC add
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Platform Management 4. IntelP®P Server Board S3420GP TPS Platform Management The platform management subsystem is based on the Integrated BMC features of the ServerEngines* Pilot II. The onboard platform management subsystem consists of communication buses, sensors, system BIOS, and server management firmware. The following diagram provides an overview of the Server Management Bus (SMBUS) architecture used on this server board. Figure 14. Server Management Bus (SMBUS) Block Diagram 4.
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IntelP®P Server Board S3420GP TPS Platform Management System event log (SEL) device functionality: The Integrated BMC supports and provides access to a SEL. Sensor device record (SDR) repository device functionality: The Integrated BMC supports storage and access of system SDRs. Sensor device and sensor scanning/monitoring: The Integrated BMC provides IPMI management of sensors. It polls sensors to monitor and report system health. IPMI interfaces.
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Platform Management IntelP®P Server Board S3420GP TPS Power unit management: Support for power unit sensor. The Integrated Baseboard Management Controller (Integrated BMC) handles power-good dropout conditions. DIMM temperature monitoring: New sensors and improved acoustic management using closed-loop fan control algorithm taking into account DIMM temperature readings.
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IntelP®P Server Board S3420GP TPS 4.2.2.3 Platform Management Availability Up to two remote KVM sessions are supported. The default inactivity timeout is 30 minutes; however, this can be changed through the embedded web server. Remote KVM activation does not disable the local system keyboard, video, or mouse. Unless the feature is disabled locally, remote KVM is not deactivated by local system input. KVM sessions persist across system reset but not across an AC power loss. 4.2.
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Platform Management 4.2.4 IntelP®P Server Board S3420GP TPS Web Services for Management (WS-MAN) The Integrated BMC firmware supports the Web Services for Management (WS-MAN) specification, version 1.0. 4.2.5 Local Directory Authentication Protocol (LDAP) The Integrated BMC firmware supports the Local Directory Authentication Protocol (LDAP) protocol for user authentication. Note that IPMI users/passwords and sessions are not supported over LDAP. 4.2.
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IntelP®P Server Board S3420GP TPS 5. 5.1 BIOS User Interface BIOS User Interface Logo / Diagnostic Screen The logo / Diagnostic Screen displays in one of two forms: z z If Quiet Boot is enabled in the BIOS setup, a logo splash screen displays. By default, Quiet Boot is enabled in the BIOS setup. If the logo displays during POST, press to hide the logo and display the diagnostic screen.
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BIOS User Interface z z IntelP®P Server Board S3420GP TPS Localization - The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard. The Intel® server board BIOS is only available in English. Console Redirection - The BIOS Setup is functional through console redirection over various terminal emulation standards.
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IntelP®P Server Board S3420GP TPS BIOS User Interface Table 10. BIOS Setup: Keyboard Command Bar Key Option Execute Command Description The key is used to activate sub-menus when the selected feature is a submenu, or to display a pick list if a selected option has a value field, or to select a sub-field for multi-valued features like time and date.
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BIOS User Interface 5.3.1.4 IntelP®P Server Board S3420GP TPS Menu Selection Bar The Menu Selection Bar is located at the top of the BIOS Setup Utility screen. It displays the major menu selections available to the user. By using the left and right arrow keys, the user can select the menus listed here. Some menus are hidden and become available by scrolling off the left or right of the current selections. 5.3.
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IntelP®P Server Board S3420GP TPS Main Advance d Security BIOS User Interface Server Management Boot Options Boot Manager Logged in as Platform ID System BIOS Version SXXXX.86B.xx.yy.zzzz Build Date Memory Total Memory Quiet Boot Enabled/Disabled POST Error Pause Enabled/Disabled System Date System Time Figure 15.
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BIOS User Interface Setup Item IntelP®P Server Board S3420GP TPS Options Help Text Size Quiet Boot Comments Information only. Displays the total physical memory installed in the system, in MB or GB. The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs. [Enabled] – Display the logo screen during POST. Enabled Disabled [Disabled] – Display the diagnostic screen during POST.
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IntelP®P Server Board S3420GP TPS Main Advance d Security BIOS User Interface Server Management Boot Options Boot Manager ► Processor Configuration ► Memory Configuration ► Mass Storage Controller Configuration ► Serial Port Configuration ► USB Configuration ► PCI Configuration ► System Acoustic and Performance Configuration Figure 16. Setup Utility – Advanced Screen Display Table 12.
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BIOS User Interface IntelP®P Server Board S3420GP TPS Advanced Processor Configuration Processor Socket Processor ID Processor Frequency Microcode Revision L1 Cache RAM L2 Cache RAM L3 Cache RAM CPU 1 Size of Cache Size of Cache Size of Cache Processor 1 Version Current QPI Link Speed QPI Link Frequency Intel® Turbo Boost Technology
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IntelP®P Server Board S3420GP TPS Setup Item Microcode Revision BIOS User Interface Options Help Text Comments Information only. Revision of the loaded microcode. L1 Cache RAM Information only. Size of the Processor L1 Cache. L2 Cache RAM Information only. Size of the Processor L2 Cache L3 Cache RAM Information only. Size of the Processor L3 Cache. Processor Version Information only. ID string from the Processor. Current QPI Link Speed Information only.
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BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Coherency Support Options Enabled Disabled Help Text Enable/Disable Intel® VT-d Coherency support. Comments Only visible when Intel® Virtualization Technology for Directed I/O is enabled. ATS Support Enabled Disabled ® Enable/Disable Intel VT-d Address Translation Services (ATS) support. Only visible when Intel® Virtualization Technology for Directed I/O is enabled.
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IntelP®P Server Board S3420GP TPS BIOS User Interface Advanced Memory Configuration Total Memory Effective Memory Current Configuration Current Memory Speed ► DIMM Information DIMM_A1 DIMM_A2 DIMM_A3 DIMM_B1 DIMM_B2 DIMM_B3
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BIOS User Interface 5.3.2.2.3 IntelP®P Server Board S3420GP TPS Setup Item Current Memory Speed Comments Information only. Displays the speed the memory is running at. DIMM_ XY Displays the state of each DIMM socket present on the board. Each DIMM socket field reflects one of the following possible states: Installed: There is a DDR3 DIMM installed in this slot. Not Installed: There is no DDR3 DIMM installed in this slot.
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IntelP®P Server Board S3420GP TPS Setup Item BIOS User Interface Options Help Text Comments Unavailable if the SAS Module (AXX4SASMOD) is not present. Note: This option is not available on some models.
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BIOS User Interface IntelP®P Server Board S3420GP TPS Advanced Serial Port Configuration Serial A Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Serial B Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Figure 20. Setup Utility – Serial Port Configuration Screen Display Table 16. Setup Utility – Serial Ports Configuration Screen Fields 5.3.2.2.5 Setup Item Serial A Enable Options Enabled Disabled Help Text Enable or Disable Serial port A.
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IntelP®P Server Board S3420GP TPS BIOS User Interface Advanced USB Configuration Detected USB Devices USB Controller Enabled / Disabled Legacy USB Support Enabled / Disabled / Auto Port 60/64 Emulation Enabled / Disabled Make USB Devices Non-Bootable Enabled / Disabled USB Mass Storage Device Configuration 10 seconds / 20 seconds / 30 seconds / 40 seconds Device Reset timeout Mass Storage Devices: Auto / Floppy/Forced FDD/Hard
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BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Device Reset timeout Options 10 sec 20 sec 30 sec 40 sec Help Text USB Mass Storage device Start Unit command timeout. Setting to a larger value provides more time for a mass storage device to be ready, if needed. Comments Grayed out if the USB Controller is disabled. One line for each mass storage device in system Auto Floppy Forced FDD Hard Disk CD-ROM [Auto] - USB devices less than 530 MB are emulated as floppies.
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IntelP®P Server Board S3420GP TPS BIOS User Interface Table 18. Setup Utility – PCI Configuration Screen Fields Setup Item Maximize Memory below 4GB Options Enabled Disabled Help Text If enabled. the BIOS maximizes usage of memory below 4 GB for OS without PAE by limiting PCIE Extended Configuration Space to 64 buses. Memory Mapped I/O above 4GB Enabled Disabled Enable or disable memory mapped I/O of 64-bit PCI devices to 4 GB or greater address space.
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BIOS User Interface IntelP®P Server Board S3420GP TPS Advanced System Acoustic and Performance Configuration Set Throttling Mode Auto / CLTT / OLTT Altitude 300m or less / 301m-900m / 901m – 1500m / Higher than 1500m Set Fan Profile Performance, Acoustic Figure 23. Setup Utility – System Acoustic and Performance Configuration Screen Display Table 19.
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IntelP®P Server Board S3420GP TPS Setup Item Set Fan Profile Options Performance Acoustics 5.3.2.3 BIOS User Interface Help Text [Performance] - Fan control provides primary system cooling before attempting to throttle memory. [Acoustic] - The system will favor using throttling of memory over boosting fans to cool the system if thermal thresholds are met. Comments This option is grayed out if CLTT is enabled. Note: This option is not available on some models.
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BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Set Administrator Password Options [123aBcD] Help Text Administrator password is used to control change access in BIOS Setup Utility. Only alphanumeric characters can be used. Maximum length is 7 characters. It is case sensitive. Note: Administrator password must be set in order to use the user account. Comments This option is only to control access to the setup. Administrator has full access to all the setup items.
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IntelP®P Server Board S3420GP TPS Advance d Main Security BIOS User Interface Server Management Boot Options Boot Manager Assert NMI on SERR Enabled / Disabled Assert NMI on PERR Enabled / Disabled Resume on AC Power Loss Stay Off / Last state / Reset Clear System Event Log Enabled / Disabled FRB-2 Enable Enabled / Disabled O/S Boot Watchdog Timer Enabled / Disabled O/S Boot Watchdog Timer Policy Power off / Reset O/S Boot Watchdog Timer Timeout ACPI 1.
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BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item O/S Boot Watchdog Timer Options Enabled Disabled Help Text If enabled, the BIOS programs the watchdog timer with the timeout value selected. If the OS does not complete booting before the timer expires, the BMC resets the system and an error is logged. Requires OS support or Intel Management Software.
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IntelP®P Server Board S3420GP TPS BIOS User Interface Table 22. Setup Utility – Console Redirection Configuration Fields Setup Item Options Help Text Console Redirection Disabled Serial Port A Serial Port B Console redirection allows a serial port to be used for server management tasks. [Disabled] - No console redirection. [Serial Port A] - Configure serial port A for console redirection. [Serial Port B] - Configure serial port B for console redirection.
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BIOS User Interface IntelP®P Server Board S3420GP TPS Server Management System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number BMC Firmware Revision HSC Firmware Revision ME Firmware Revision SDR Revision UUID Figure 27. Setup Utility – Server Management System Information Screen Display Table 23. Setup Utility – Server Management System Information Fields 5.3.2.
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IntelP®P Server Board S3420GP TPS Main Advance d Security BIOS User Interface Server Management Boot Options System Boot Timeout <0 - 65535> Boot Option #1 Boot Option #2 Boot Option #x Boot Manager Hard Disk Order CDROM Order Network Device Order ►Delete Boot Option EFI Optimized Boot Enabled / Disabled Boot Option Retry Enabled / Disabled Figure 28. Setup Utility – Boot Options Screen Display Table 24.
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BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Network Device Order Options Help Text Set the order of the legacy devices in this group. Comments Visible when one or more of these devices are available in the system. BEV Device Order Set the order of the legacy devices in this group. Visible when one or more of these devices are available in the system. Add New Boot Option Add a new EFI boot option to the boot order.
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IntelP®P Server Board S3420GP TPS Setup Item Delete Boot Option 5.3.2.6.2 BIOS User Interface Options Select one to Delete Internal EFI Shell Help Text Remove an EFI boot option from the boot order. Hard Disk Order Screen The Hard Disk Order screen allows the user to control the hard disks. To access this screen from the Main screen, choose Boot Options > Hard Disk Order. Boot Options Hard Disk #1 < Available Hard Disks > Hard Disk #2 < Available Hard Disks > Figure 30.
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BIOS User Interface 5.3.2.6.4 IntelP®P Server Board S3420GP TPS Setup Item CDROM #1 Options Available Legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. CDROM #2 Available Legacy devices for this Device group. Set system boot order by selecting the boot option for this position. Floppy Order Screen The Floppy Order screen allows the user to control the floppy drives.
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IntelP®P Server Board S3420GP TPS BIOS User Interface Table 29. Setup Utility – Network Device Order Fields Setup Item Network Device #1 Options Available Legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. Network Device #2 Available Legacy devices for this Device group. Set system boot order by selecting the boot option for this position. 5.3.2.
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BIOS User Interface IntelP®P Server Board S3420GP TPS • Moving the clear system configuration jumper. • IPMI command (set System Boot options command) • Int15 AX=DA209 • Choosing Load User Defaults from the Exit page of the BIOS Setup loads user set defaults instead of the BIOS factory defaults. The recommended steps to load the BIOS defaults are: 1. Power down the system (Do not remove AC power). 2. Move the Clear CMOS jumper from pins 1-2 to pins 2-3. 3.
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IntelP®P Server Board S3420GP TPS 6. 6.1 Connector/Header Locations and Pin-outs Connector / Header Locations and Pin-outs Board Connector Information The following section provides detailed information regarding all connectors, headers, and jumpers on the server board. It lists all connector types available on the board and the corresponding reference designators printed on the silkscreen. Table 31.
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Connector/Header Locations and Pin-outs IntelP®P Server Board S3420GP TPS One SSI-compliant 2x4 pin power connector (J9C1), which provides 12-V power to the CPU VRD. The following tables define the connector pin-outs. Table 32. Baseboard Power Connector Pin-out (J9A1) Pin Signal Color Pin Signal Color 1 +3.3 Vdc Orange 13 +3.3 Vdc Orange 2 +3.
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IntelP®P Server Board S3420GP TPS Pin Connector/Header Locations and Pin-outs 1 Signal Name P3V3_AUX 2 Signal Name RMII_IBMC_RMM3_MDIO 3 P3V3_AUX 4 RMII_IBMC_RMM3_MDC 5 GND 6 RMII_IBMC_RMM3_RXD1 7 GND 8 RMII_IBMC_RMM3_RXD0 9 GND 10 RMII_IBMC_RMM3_CRS_DV 11 GND 12 CLK_50M_RMM3 13 GND 14 RMII_IBMC_RMM3_RX_ER 15 GND 16 RMII_IBMC_RMM3_TX_EN 17 GND 18 KEY 19 GND 20 RMII_IBMC_RMM3_TXD0 21 GND 22 RMII_IBMC_RMM3_TXD1 23 P3V3_AUX 24 SPI_IBMC_BK_CS_N 25 P3V3_AUX 26
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Connector/Header Locations and Pin-outs 2 3 4 6.4 IntelP®P Server Board S3420GP TPS SGPIO_LOAD SGPIO_DATAOUT0 SGPIO_DATAOUT1 SGPIO Load Signal SGPIO Data Out SGPIO Data In Front Control Panel Connector The server board provides a 24-pin SSI front panel connector (J1C1) for use with Intel® and third-party chassis. The following table provides the pin-out for this connector. Table 38.
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IntelP®P Server Board S3420GP TPS Connector/Header Locations and Pin-outs power state signals from the chipset and de-asserts PS_PWR_ON to the power supply. As a safety mechanism, if the BIOS fails to service the request, the Integrated BMC automatically powers off the system in 4 to 5 seconds. Power Button — On to Off (Operating system present) If an ACPI operating system is running, pressing the power button switch generates a request using SCI to the operating system to shut down the system.
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Connector/Header Locations and Pin-outs IntelP®P Server Board S3420GP TPS Table 39. System Status LED Indicator States Color Green Green Amber Amber Off State Solid on ~1 Hz blink ~1 Hz blink Solid on N/A Criticality Ok Degraded Non-critical Critical, nonrecoverable Not ready Description System booted and ready System degraded: Non-critical temperature threshold asserted. Non-critical voltage threshold asserted. Non-critical fan threshold asserted.
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IntelP®P Server Board S3420GP TPS 6.5 Connector/Header Locations and Pin-outs I/O Connectors 6.5.1 VGA Connector The following table details the pin-out definition of the VGA connector (J7A1). Table 40. VGA Connector Pin-out (J7A1) Pin 6.5.
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Connector/Header Locations and Pin-outs 6.5.
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IntelP®P Server Board S3420GP TPS Connector/Header Locations and Pin-outs Table 45. External Serial A Port Pin-out (J8A1) 1 Pin Signal Name SPA_DCD Description DCD (carrier detect) 2 SPA_SIN_L RXD (receive data) 3 SPA_SOUT_N TXD (Transmit data) 4 SPA_DTR DTR (Data terminal ready) 5 GND Ground 6 SPA_DSR DSR (data set ready) 7 SPA_RTS RTS (request to send) 8 SPA_CTS CTS (clear to send) 9 SPA_RI RI (Ring Indicate) 10 NC Table 46.
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Connector/Header Locations and Pin-outs IntelP®P Server Board S3420GP TPS Table 47.
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IntelP®P Server Board S3420GP TPS 6.6 Connector/Header Locations and Pin-outs PCI Express* Slot / PCI Slot / Riser Card Slot / A PCI-E Riser card will enable a PCI-E add-on card to be accommodated in the 1U chassis. The following table shows the pin-out for this riser slot. Table 50. Pin-out of adaptive riser slot / PCI Express slot 6 Pin Signal Description Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 +12V +12V RSVD GND SMCLK SMDATA GND +3.3V JTAG1 +3.
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Connector/Header Locations and Pin-outs B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 GND GND PETP6 PETN6 GND GND PETP7 PETN7 GND PRSNT2_N GND GND GND P2E_CPU_C_S6_TXP<1> P2E_CPU_C_S6_TXN<1> GND GND P2E_CPU_C_S6_TXP<0> P2E_CPU_C_S6_TXN<0> GND NC GND B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 PETP8 PETN8 GND GND PETP9 PETN9 GND GND PETP10 PETN10 GND GND PExP11 PETN11 GND GND PETP12 PETN12 GND GND PETP13 PETN13 GND GND
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IntelP®P Server Board S3420GP TPS Connector/Header Locations and Pin-outs Three PCI Express* x8 connectors (J2B2, J3B1 and J4B2) Pin Signal Pin Signal Pin Signal Pin Signal A1 PRSNT1# B1 +12V A26 HSIP[2] B26 GND A2 +12V B2 +12V A27 GND B27 HSOP[3] A3 +12V B3 RESERVED A28 GND B28 HSON[3] A4 GND B4 GND A29 HSIP[3] B29 GND A5 JTAG2/TCk B5 SMCLK A30 HSIN[3] B30 RESERVED A6 JTAG3/TDI B6 SMDAT A31 GND B31 PRSNT2# A7 JTAG4/TDO B7 GND A32 RESERVED B32
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Connector/Header Locations and Pin-outs IntelP®P Server Board S3420GP TPS Pin# Signal Pin# Signal Pin# Signal Pin# Signal A5 JTAG2 B5 SMCLK A21 PERP1 B21 GND A6 JTAG3 B6 SMDAT A22 PERN1 B22 GND A7 JTAG4 B7 GND A23 GND B23 PETP2 A8 JTAG5 B8 +3.3V A24 GND B24 PETN2 A9 +3.3V B9 JTAG1 A25 PERP2 B25 GND A10 +3.3V B10 3.
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IntelP®P Server Board S3420GP TPS 6.7 Connector/Header Locations and Pin-outs Pin # Signal Pin # Signal Pin # Signal B26 C/BE[3]# A26 B27 AD[23] A27 B28 Ground A28 Pin # Signal IDSEL B57 +3.3V B58 Ground A57 AD[02] AD[01] A58 AD[22] AD[00] B59 V_IO A59 V_IO B29 AD[21] A29 AD[20] B60 ACK64# A60 REQ64# B30 AD[19] A30 Ground B61 +5V A61 +5V B31 +3.
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Jumper Blocks 7. IntelP®P Server Board S3420GP TPS Jumper Blocks The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Figure 35. Jumper Blocks (J1A2, J1F1, J1F3, J1F2 and J1F5) Table 52.
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IntelP®P Server Board S3420GP TPS Jumper Name Force Update 7.1 Pins 2-3 Jumper Blocks System Results Integrated BMC Firmware Force Update Mode – Enabled CMOS Clear and Password Reset Usage Procedure The CMOS Clear (J1F5) and Password Reset (J1F2) recovery features are designed such that the desired operation can be achieved with minimal system downtime. The usage procedure for these two features has changed from previous generation Intel server boards.
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Jumper Blocks IntelP®P Server Board S3420GP TPS 7. Open the chassis and move the jumper back to the default position (covering pins 1 and 2). 8. Close the server chassis. 9. Power up the server. The password is now cleared and can be reset by going into the BIOS setup. 7.
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IntelP®P Server Board S3420GP TPS Jumper Blocks firmware update process fails due to ME not being in the proper update state, the server board provides an Integrated BMC Force Update jumper (J1F1), which forces the ME into the proper update state. The following procedure should be completed in the event the standard ME firmware update process fails. 1. Power down and remove the AC power cord. 2. Open the server chassis. For instructions, see your server chassis documentation. 3.
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Intel® Light Guided Diagnostics 8. IntelP®P Server Board S3420GP TPS Intel® Light Guided Diagnostics The server board has several on-board diagnostic LEDs to assist in troubleshooting board-level issues. This section shows where each LED is located on the server board and describes the function of each LED. 8.1 System Status LED The server board provides a system status indicator LED on the front panel.
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IntelP®P Server Board S3420GP TPS 8.2 Intel® Light Guided Diagnostics Post Code Diagnostic LEDs During the system boot process, the BIOS executes several platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code on the POST code diagnostic LEDs found on the back edge of the server board.
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Design and Environmental Specifications 9. 9.1 IntelP®P Server Board S3420GP TPS Design and Environmental Specifications Intel® Server Board S3420GP Design Specifications The operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 55.
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IntelP®P Server Board S3420GP TPS 9.3 Design and Environmental Specifications Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel® Server Board S3420GP, including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the power distribution implemented on this server board. Figure 36. Power Distribution Block Diagram Revision 1.
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Design and Environmental Specifications 9.3.1 IntelP®P Server Board S3420GP TPS Processor Power Support The server board supports the Thermal Design Power (TDP) guideline for Intel® Xeon® processor. The Flexible Motherboard Guidelines (FMB) were also followed to help determine the suggested thermal and current design values for anticipating future processor needs. The following table provides maximum values for Icc, TDP power and TCASE for the Intel® Xeon® 3400 Series processor. Table 56.
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IntelP®P Server Board S3420GP TPS 9.4.1 Design and Environmental Specifications Grounding The grounds of the power supply output connector pins provide the power return path. The output connector ground pins are connected to the safety ground (power supply enclosure). This grounding is designed to ensure passing the maximum allowed common mode noise levels. The power supply is provided with a reliable protective earth ground. All secondary circuits are connected to protective earth ground.
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Design and Environmental Specifications +5 VSB Notes: 1. 9.4.6 0.5 A IntelP®P Server Board S3420GP TPS 20 µF 0.25 A/µsec Step loads on each 12 V output may happen simultaneously and should be tested that way. Capacitive Loading The power supply is stable and meets all requirements with the following capacitive loading ranges. Table 60. Capacitve Loading Conditions 9.4.7 Output +3.
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IntelP®P Server Board S3420GP TPS Design and Environmental Specifications The output voltages must rise from 10% to within regulation limits (Tvout_rise) within 5 ms to 70 ms, except for 5 VSB, in which case it is allowed to rise from 1.0 ms to 25 ms. The +3.3 V, +5 V, and +12 V output voltages should start to rise approximately at the same time. All outputs must rise monotonically. The +5 V output must be greater than the +3.3 V output during any point of the voltage rise.
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Design and Environmental Specifications IntelP®P Server Board S3420GP TPS Table 63. Turn On/Off Timing Item Tsb_on_delay Tac_on_delay Tvout_holdup Tpwok_holdup Tpson_on_delay Tpson_pwok Tpwok_on Tpwok_off Tpwok_low Tsb_vout T5VSB_holdup Description Delay from AC being applied to 5 VSB being within regulation. Delay from AC being applied to all output voltages being within regulation. Duration for which all output voltages stay within regulation after loss of AC. Measured at 80% of maximum load.
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IntelP®P Server Board S3420GP TPS 9.4.11 Design and Environmental Specifications Residual Voltage Immunity in Standby Mode The power supply is immune to any residual voltage placed on its outputs (typically, a leakage voltage through the system from standby output) up to 500 mV. There is no additional heat generated nor stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously.
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Design and Environmental Specifications IntelP®P Server Board S3420GP TPS +5 V 5.7 6.2 +12 V 13.3 14.5 -12 V -13.3 -14.5 +5 VSB 5.7 6.5 Revision 1.
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IntelP®P Server Board S3420GP TPS Regulatory and Certification Information 10. Regulatory and Certification Information 10.1 Product Regulatory Compliance Intended Application –This product is to be evaluated and certified as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations.
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Regulatory and Certification Information FCC/ICES-003 Class A Attestation (USA/Canada) C-Tick Declaration of Conformity (Australia) MED Declaration of Conformity (New Zealand) BSMI Declaration (Taiwan) RRL Certification (Korea) GOST – Listed on one System License (Russia) Belarus – Listed on one System License (Belarus) Ecology Declaration (International) IntelP®P Server Board S3420GP TPS 10.1.
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IntelP®P Server Board S3420GP TPS Regulatory and Certification Information 10.2 Product Regulatory Compliance Markings The server board is provided with the following regulatory marks.
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Regulatory and Certification Information Other Recycling Package Marking (Marked on packaging label) Other Recycling Package Marks Other Recycling Package Marking (Marked on packaging label) CA. Lithium Perchlorate insert IntelP®P Server Board S3420GP TPS Perchlorate Material – Special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate This notice is required by California Code of Regulations, Title 22, Division 4.5, Chapter 33: Best Management Practices for Perchlorate Materials.
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IntelP®P Server Board S3420GP TPS Regulatory and Certification Information 10.3 Electromagnetic Compatibility Notices 10.3.1 FCC Verification Statement (USA) This device complies with Part 15 of the FCC Rules. Operation is subject to two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Intel Corporation 5200 N.E.
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Regulatory and Certification Information IntelP®P Server Board S3420GP TPS 10.3.2 ICES-003 (Canada) Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur: “Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications.
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IntelP®P Server Board S3420GP TPS Regulatory and Certification Information 10.3.5 BSMI (Taiwan) The BSMI Certification Marking and EMC warning is located on the outside rear area of the product. 10.3.6 RRL (Korea) Following is the RRL certification information for Korea. English translation of the notice above: 1. 2. 3. 4. 5. Type of Equipment (Model Name): On License and Product Certification No.: On RRL certificate.
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Appendix A: Integration and Usage Tips IntelP®P Server Board S3420GP TPS Appendix A: Integration and Usage Tips When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-Volt standby is still present even though the server board is powered off. Supports only Intel® Xeon® 3400 Series processor with 95 W and less Thermal Design Power (TDP). Does not support previous generations of the Intel® Xeon® processor.
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IntelP®P Server Board S3420GP TPS Appendix B: Integrated BMC Sensor Tables Appendix B: Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event/reading-type table information.
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Appendix B: Integrated BMC Sensor Tables IntelP®P Server Board S3420GP TPS Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor.
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IntelP®P Server Board S3420GP TPS Appendix B: Integrated BMC Sensor Tables Table 66. Integrated BMC Core Sensors Sensor Name3 IPMI Watchdog Sensor # 03h Platform Applicabilit y All Sensor Type Event / Reading Type Watchdog 2 23h Sensor Specific 6Fh Event Offset Triggers Contrib.
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Appendix B: Integrated BMC Sensor Tables Sensor Name3 BB +1.1V P1 Vccp BB +1.1V P2 Vccp BB +1.5V P1 DDR3 BB +1.5V P2 DDR3 BB +1.8V AUX BB +3.
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IntelP®P Server Board S3420GP TPS Sensor Name3 BB +5.0V BB +5.0V STBY BB +12.0V BB -12.
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Appendix B: Integrated BMC Sensor Tables Sensor Name3 IntelP®P Server Board S3420GP TPS Sensor # Platform Applicabilit y Sensor Type Event / Reading Type Fan Tach Sensors 30h– 34h Chassisspecific Fan Threshold 04h 01h Processor Therm Margin 62h All Temperatur e Threshold Processor Therm Ctrl % 01h 64h All Temperatur e 01h Processor VRD Temp CATERR PCH Thermal Trip 66h 68h 6Ah All All All 01h Threshold 01h Temperatur e Digital Discrete 01h 05h Processor Digital Discrete
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IntelP®P Server Board S3420GP TPS Appendix C: POST Code Diagnostic LED Decoder Appendix C: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board.
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Appendix C: POST Code Diagnostic LED Decoder MSB 8h 4h LED #7 #6 Host Processor 0x04h X X 0x10h X X 0x11h X X 0x12h X X 0x13h X X Chipset 0x21h X X Memory 0x22h X X 0x23h X X 0x24h X X 0x25h X X 0x26h X X 0x27h X X 0x28h X X PCI Bus 0x50h X O 0x51h X O 0x52h X O 0x53h X O 0x54h X O 0x55h X O 0x56h X O 0x57h X O USB 0x58h X O 0x59h X O ATA/ATAPI/SATA 0x5Ah X O 0x5Bh X O 0x5Ch X O 0x5Dh X O SMBUS 0x5Eh X O 0x5Fh X O Local Console 0x70h X O 0x71h X O 0x72h X O Remote Console 0x78h X O 0x79h X O 0x7Ah X O Keyb
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IntelP®P Server Board S3420GP TPS Appendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder O = On, X=Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 0x93h O X X O X X O O 0x94h O X X O X O X X 0x95h O X X O X O X O Mouse (only USB) 0x98h O X X O X X O X 0x99h O X X O X X O O 0x9Ah O X X O X O O X 0x9Bh O X X O X O O O Fixed Media 0xB0h O X O O X X X X 0xB1h O X O O X X X O 0xB2h O Description Enabling the keyboard Clearing keyboard input b
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Appendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder O = On, X=Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 Pre-EFI Initialization Module (PEIM) / Recovery 0x30h X X O O X X X X 0x31h X X O O X X X O 0x34h X X O O X O X X 0x35h X X O O X O X O 0x3Fh X X O O O O O O Runtime Phase / EFI Operating System Boot 0XF2h IntelP®P Server Board S3420GP TPS Description Crisis recovery has been initiated because of a user request Crisis recovery
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IntelP®P Server Board S3420GP TPS Appendix D: POST Code Errors Appendix D: POST Code Errors Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity.
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Appendix D: POST Code Errors IntelP®P Server Board S3420GP TPS Error Code 8111 Error Message Processor 02 internal error (IERR) on last boot Pause Response 8120 Processor 01 thermal trip error on last boot Pause 8121 Processor 02 thermal trip error on last boot Pause 8130 Processor 01 disabled Pause 8131 Processor 02 disabled Pause 8140 Processor 01 Failed FRB-3 Timer. No Pause 8141 Processor 02 Failed FRB-3 Timer.
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IntelP®P Server Board S3420GP TPS Appendix D: POST Code Errors Error Code 8549 DIMM_C2 Disabled. Error Message Pause Response 854A DIMM_C3 Disabled. Pause 854B DIMM_C4 Disabled. Pause 854C DIMM_D1 Disabled. Pause 854D DIMM_D2 Disabled. Pause 854E DIMM_D3 Disabled. Pause 854F DIMM_D4 Disabled. Pause 8560 DIMM_A1 Component encountered a Serial Presence Detection (SPD) fail error. Pause 8561 DIMM_A2 Component encountered a Serial Presence Detection (SPD) fail error.
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Appendix D: POST Code Errors IntelP®P Server Board S3420GP TPS Error Code 85A7 Error Message DIMM_B4 Uncorrectable ECC error encountered. Pause Response 85A8 DIMM_C1 Uncorrectable ECC error encountered. Pause 85A9 DIMM_C2 Uncorrectable ECC error encountered. Pause 85AA DIMM_C3 Uncorrectable ECC error encountered. Pause 85AB DIMM_C4 Uncorrectable ECC error encountered. Pause 85AC DIMM_D1 Uncorrectable ECC error encountered. Pause 85AD DIMM_D2 Uncorrectable ECC error encountered.
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IntelP®P Server Board S3420GP TPS Appendix D: POST Code Errors Error Code 0xA500 Error Message ATA/ATPI ATA bus SMART not supported. Response No Pause 0xA501 ATA/ATPI ATA SMART is disabled. No Pause 0xA5A0 PCI Express* component encountered a PERR error. No Pause 0xA5A1 PCI Express* component encountered a SERR error. Halt 0xA5A4 PCI Express* IBIST error. Pause 0xA6A0 DXE boot services driver Not enough memory available to shadow a legacy option ROM.
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Appendix E: Supported IntelP®P Server Chassis IntelP®P Server Board S3420GP TPS Appendix E: Supported Intel® Server Chassis P P The Intel® Server Board S3420GP is supported in the following Intel server chassis: P P Intel® Server Chassis SR1630 P P ® Intel Server Chassis SC5650UP P P Revision 1.
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IntelP®P Server Board S3420GP TPS Glossary Glossary This appendix contains important terms used in this document. For ease of use, numeric entries are listed first (for example, “82460GX”) followed by alpha entries (for example, “AGP 4x”). Acronyms are followed by non-acronyms.
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Glossary IntelP®P Server Board S3420GP TPS Term Definition ICH I/O Controller Hub ICMB Intelligent Chassis Management Bus IERR Internal Error IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt I/OAT I/O Acceleration Technology IOH I/O Hub IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Target Probe KB 1024 bytes KCS Keyboard Controller
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IntelP®P Server Board S3420GP TPS Term PSMI Power Supply Management Interface PWM Pulse-Width Modulation QPI QuickPath Interconnect RAM Random Access Memory Glossary Definition RASUM Reliability, Availability, Serviceability, Usability, and Manageability RISC Reduced Instruction Set Computing RMII Reduced Media-Independent Interface ROM Read Only Memory RTC Real-Time Clock (Component of ICH peripheral chip on the server board) SDR Sensor Data Record SECC Single Edge Connector Cartrid
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Reference Documents IntelP®P Server Board S3420GP TPS Reference Documents Refer to the following documents for additional information: Intel® Server Board S3420GP BIOS External Product Specification P P ® Intel Server Board S3420GP Common Core Integrated BMC External Product Specification P P Revision 1.