System Service Guide

Appendix C: LED Decoder

Table 13. MRC Progress Codes

Progress Code Main Sequence Subsequences/Subfunctions

0xB0 Detect DIMM population —n/a—

0xB1 Set DDR3 frequency —n/a—

0xB2 Gather remaining SPD data —n/a—

0xB3 Program registers on the memory controller level —n/a—

0xB4 Evaluate RAS modes and save rank information —n/a—

0xB5 Program registers on the channel level —n/a—

0xB6 Perform the JEDEC defined initialization sequence —n/a—

0xB7 Train DDR3 ranks —n/a—

0x01  Read DQ/DQS training

0x02  Receive Enable training

0x03  Write Leveling training

0x04  Write DQ/DQS training

0x05  DDR channel training done

0xB8 Initialize CLTT/OLTT —n/a—

0xB9 Hardware memory test and init —n/a—

0xBA Execute software memory init —n/a—

0xBB Program memory map and interleaving —n/a—

0xBC Program RAS configuration —n/a—

0xBF MRC is done —n/a—

Intel

Server System H2000WP Family Service Guide 65