Technical Product Specification

Platform Management Functional Overview Intel
®
Server Board S2600WP TPS
4.14.4
BMC – Management Engine Interaction
Management Engine-Integrated BMC interactions include the following:
 Integrated BMC stores sensor data records for ME-owned sensors.
 Integrated BMC participates in ME firmware update.
 Integrated BMC initializes ME-owned sensors based on SDRs.
 Integrated BMC receives platform event messages sent by the ME.
 Integrated BMC notifies ME of POST completion.
 BMC may be queried by the ME for inlet temperature readings
4.14.5
ME Power and Firmware Startup
On Intel
®
Server Board S2600WP, the ME is on standby power. The ME FW will begin its
startup sequence at the same time that the BMC FW is booting. As the BMC FW is booting to a
Linux* kernel and the ME FW uses an RTOS, the ME FW should always complete its basic
initialization before the BMC. The ME FW can be configured to send a notification message to
the BMC. After this point, the ME FW is ready to process any command requests from the BMC.
In S0/S1 power states, all ME FW functionality is supported. Some features, such as power
limiting, are not supported in S3/S4/S5 power states. Refer to ME FW documentation for details
on what is not supported while in the S3/S4/S5 states.
The ME FW uses a single operational image with a limited-functionality recovery image. In order
to upgrade an operational image, a boot to recovery image must be performed. The ME FW
does not support an IPMI update mechanism except for the case that the system is configured
with a dual-ME (redundant) image. In order to conserve flash space, which the ME FW shares
with BIOS, Intel
®
Server Boards and Systems only support a single ME image. For this case,
ME update is only supported by means of BIOS performing a direct update of the flash
component. The recovery image only provides the basic functionality that is required to perform
the update; therefore other ME FW features are not functional therefore when the update is in
progress.
4.14.6
SmaRT/CLST
The power supply optimization provided by SmaRT/CLST relies on a platform HW capability as
well as ME FW support. When a PMBus*-compliant power supply detects insufficient input
voltage, an over current condition, or an over-temperature condition, it will assert the SMBAlert#
signal on the power supply SMBus* (also known as the PMBus*).
Through the use of external
gates, this results in a momentary assertion of the PROCHOT# and MEMHOT# signals to the
processors, thereby throttling the processors and memory. The ME FW also sees the
SMBAlert# assertion, queries the power supplies to determine the condition causing the
assertion, and applies an algorithm to either release or prolong the throttling, based on
the situation.
System power control modes include:
 SmaRT: Low AC input voltage event; results in a onetime momentary throttle for each
event to the maximum throttle state
 Electrical Protection CLST: High output energy event; results in a throttling hiccup
mode with fixed maximum throttle time and a fix throttle release ramp time.
Intel order number G44057-007 Revision 1.6
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