Technical Product Specification

Intel
®
Server Board S2600WP TPS Platform Management Functional Overview
which may log these into the system SEL and/or output them to the remote application in the
form of IPMI LAN alerts.
The ServerEngines* Pilot III BMC needs access to various system registers in the processor
core silicon and integrated memory controller subsystem.
Examples include Processor core and
Memory DIMMs temperature information.
The ServerEngines* Pilot III BMC requires this
information as input into its fan speed control algorithms.
The ServerEngines* Pilot III BMC
accesses these registers through the secondary IPMB bus connection to ME. Depending on the
particular data or register access needed, this is done using either the ME’s PECI proxy
functionality or through an abstracted data construct provided by the ME.
Also in this architecture, both the ServerEngines* Pilot III BMC and the ME are connected to the
system power supplies through a common PMBus* (SMBus* physical) connection (SMLINK 1.)
The ME accesses the system power supplies in support of various NM 2.0 features. The
ServerEngines* Pilot III BMC monitors the power supplies in support of various power-related
telemetry and status information that is exposed as IPMI sensors.
Figure 22. Management Engine Distribution Model
4.14.3
ME System Management Bus (SMBus*) Interface
 The ME uses the SMLink0 on the SSB in multi-master mode as a dedicated bus for
communication with the BMC using the IPMB protocol. The BMC FW considers this a
secondary IPMB bus and runs at 400KHz.
 The ME uses the SMLink1 on the SSB in multi-master mode bus for communication with
PMBus* devices in the power supplies for support of various NM-related features. This
bus is shared with the BMC, which polls these PMBus* power supplies for sensor
monitoring purposes (for example power supply status, input power, and so on.). This
bus runs at 100 KHz.
 The Management Engine has access to the “Host SMBus*”.
Revision 1.6 Intel order number G44057-007 63