Technical Product Specification

Platform Management Functional Overview Intel
®
Server Board S2600WP TPS
4.2
Advanced Configuration and Power Interface (ACPI)
The server board has support for the following ACPI states:
Table 15. ACPI Power States
State
Supported
Description
S0
Yes
Working.
 The front panel power LED is on (not controlled by the BMC).
 The fans spin at the normal speed, as determined by sensor inputs.
 Front panel buttons work normally.
S1
Yes
Sleeping. Hardware context is maintained; equates to processor and chipset clocks being
stopped.
 The front panel power LED blinks at a rate of 1 Hz with a 50% duty cycle (not controlled
by the BMC).
 The watchdog timer is stopped.
 The power, reset, front panel NMI, and ID buttons are unprotected.
 Fan speed control is determined by available SDRs. Fans may be set to a fixed state, or
basic fan management can be applied.
The BMC detects that the system has exited the ACPI S1 sleep state when the BIOS SMI
handler notifies it.
S2
No
Not supported.
S3
No
Supported only on Workstation platforms. See appropriate Platform Specific Information for
more information.
S4
No
Not supported.
S5
Yes
Soft off.
 The front panel buttons are not locked.
 The fans are stopped.
 The power-up process goes through the normal boot process.
 The power, reset, front panel NMI, and ID buttons are unlocked.
4.3
Platform Management SMBus* and I
2
C Implementation
SMBus*/I
2
C interconnections are a fundamental interface for various manageability components.
There are three busses that are used in a multi-master fashion.
 Primary IPMB. An IPMB header is provided on the baseboard to support connectivity
with 3
rd
party management PCIe cards. This bus operates as 100 kHz bus.
 Secondary IPMB. This is the SMLink0 bus that connects the BMC with the ME in the
SSB. This bus is considered a secondary IPMB. The ME and BMC communicate over
this bus using IPMB protocol messages. This bus runs at close to 400 kHz (due to a
C600 chipset SSB constraint, it cannot achieve a full 400 kHz operation). Any devices on
the bus must be compatible with a 400 kHz bus speed.
 PMBus*. This is the SMLink1 bus that both the ME and BMC use to communicate with
the power supplies. This bus operates as 100 kHz bus.
For all multi-master busses, the master that initiates a transaction is responsible for any bus
recovery sequence if the bus hangs.
Intel order number G44057-007 Revision 1.6
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