Technical Product Specification

Product Architecture Overview Intel
®
Server Board S2600WP TPS
Figure 18. ConnectX-3* function block diagram
Major features and functions include:
 Single InfiniBand* Port: SDR/DDR/QDR on S2600WPQ, SDR/DDR/QDR/FDR on
S2600WPF with port remapping in firmware
 Performance optimization: achieving single port line-rate bandwidth
 PCI Express* 3.0 x8 to achieve 2.5, 5 or 8GT/s link rate
 Optimized for LOM: Small footprint, minimal peripherals, WOL, integrated sensors,
and BMC interface
 Low power consumption: 6.5Watt typical
3.5.1
Device Interfaces
Below is a list of major interfaces of Mellanox* ConnectX-3* chip:
 Clock and Reset signals: Include core clock input and chip reset signals.
 Uplink Bus: The PCI Express* bus is a high-speed uplink interface used to connect
Mellanox* ConnectX-3* to the host processor. The Mellanox* ConnectX-3* supports
a PCI Express* 3.0 x8 uplink connection with transfer rates of 2.5GT/s, 5GT/s and
8GT/s per lane. Throughout this document, the PCI Express* interface may also be
referred to as the “uplink” interface.
 Network Interface: Single network port connecting the device to a network fabric in
one of the configurations described in below table.
Table 12. Network port configuration
Port Configured as
10/20/40/56 Gb/s InfiniBand*
 Flash interface: Chip initialization and host boot.
Intel order number G44057-007 Revision 1.6
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