Technical Product Specification

Intel
®
Server Board S2600WP TPS Product Architecture Overview
3.4.7
Digital Media Interface (DMI)
Digital Media Interface (DMI) is the chip-to-chip connection between the processor and Intel
®
C600-A PCH. This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely
software-transparent, permitting current and legacy software to operate normally.
3.4.8
Serials Peripheral Interface (SPI)
The Intel
®
C600-A PCH implements an SPI Interface as an alternative interface for the BIOS
flash device. An SPI flash device can be used as a replacement for the FWH, and is required to
support Gigabit Ethernet and Intel
®
Active Management Technology. The PCH supports up to
two SPI flash devices with speeds up to 50 MHz, utilizing two chip select pins.
3.4.9
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers. Channel 4 is
reserved as a generic bus master request.
The Intel
®
C600-A PCH supports LPC DMA, which is similar to ISA DMA, through the PCH’s
DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and
special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are
supported on the LPC interface.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock
source for these three counters.
The Intel
®
C600-A PCH provides an ISA-Compatible Programmable Interrupt Controller (PIC)
that incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In addition,
the PCH supports a serial interrupt scheme. All of the registers in these modules can be read
and restored. This is required to save and restore system state after power has been removed
and restored to the platform.
3.4.10
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA compatible Programmable Interrupt Controller (PIC) described in
the previous section, the Intel
®
C600-A PCH incorporates the Advanced Programmable
Interrupt Controller (APIC).
3.4.11
Real Time Clock (RTC)
The Intel
®
C600-A PCH contains a Motorola* MC146818B-compatible real-time clock with 256
bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of
the time of day and storing system data, even when the system is powered down. The RTC
operates on a 32.768KHz crystal and a 3V battery. The RTC also supports two lockable
memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to
read and write accesses. This prevents unauthorized reading of passwords or other system
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