Technical Product Specification

Product Architecture Overview Intel

Server

Board S2600WP TPS

3.3.2.4.4

Lockstep Channel Mode

In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel 0

and Channel 1, and Channel 2 and Channel 3. Lockstep Channel mode is the only RAS mode

that allows SDDC for x8 devices. Lockstep Channel Mode requires that Channel 0 and Channel

1, and Channel 2 and Channel 3 must be populated identically with regards to size and

organization. DIMM slot populations within a channel do not have to be identical but the same

DIMM slot location across Channel 0 and Channel 1 and across Channel 2 and Channel 3 must

be populated the same.

3.3.3

Processor Intergrated I/O Module (I/O)

The processor’s integrated I/O module provides features traditionally supported through chipset

components. The integrated I/O module provides the following features:

 PCI Express* Interfaces: The integrated I/O module incorporates the PCI Express*

interface and supports up to 40 lanes of PCI Express*. Following are key attributes of

the PCI Express* interface:

o Gen3 speeds at 8 GT/s (no 8b/10b encoding)

o X16 interface bifurcated down to two x8 or four x4 (or combinations)

o X8 interface bifurcated down to two x4

 DMI2 Interface to the PCH: The platform requires an interface to the legacy

Southbridge (PCH) which provides basic, legacy functions required for the server

platform and operating systems. Since only one PCH is required and allowed for the

system, any sockets which do not connect to PCH would use this port as a standard x4

PCI Express* 2.0 interface.

 Integrated IOAPIC: Provides support for PCI Express* devices implementing legacy

interrupt messages without interrupt sharing.

 Non Transparent Bridge: PCI Express* non-transparent bridge (NTB) acts as a

gateway that enables high performance, low overhead communication between two

intelligent subsystems; the local and the remote subsystems. The NTB allows a local

processor to independently configure and control the local subsystem, provides isolation

of the local host memory domain from the remote host memory domain while enabling

status and data exchange between the two domains.

 Intel

QuickData Technology: Used for efficient, high bandwidth data movement

between two locations in memory or from memory to I/O.

Intel order number G44057-007 Revision 1.6