Technical Product Specification

Intel
®
Server Board S2600WP TPS Product Architecture Overview
Notes:
1. Supported DRAM Densities are 1Gb, 2Gb, and 4Gb. Only 2Gb and 4Gb are validated by Intel.
2. Command Address Timing is 1N.
3. QR RDIMMs are supported but only validated by Intel in a homogenous environment. The coverage will
have limited system level testing, no signal integrity testing, and no interoperability testing. The passing QR
RDIMMs will be web posted.
Table 7. LRDIMM Support Guidelines
Ranks Per DIMM and
Data Width
1
Memory Capacity Per
DIMM
2
Speed (MT/s) and Voltage Validated by
Slot Per Channel (SPC) and DIMM Per Channel (DPC)
3,4,5
2 Slots Per Channel
1DPC
2DPC
1.35V
1.5V
1.35V
1.5V
QRx4
(DDP)
16GB 32GB
1066, 1333,
1600
1066, 1333,
1600,1866
1066, 1333,
1600
1066, 1333,
1600
Notes:
1. Physical Rank is used to calculate DIMM Capacity.
2. Supported and validated DRAM Densities are 2Gb and 4Gb.
3. Command Address Timing is 1N.
4. For 3SPC/3DPC – Rank Multiplication (RM) >= 2.
5. DDP – Dual Die Package DRAM stacking. P – Planer monolithic DRAM Die.
3.3.2.2
Memory Population Rules
Note: Although mixed DIMM configurations are supported, Intel only performs platform
validation on systems that are configured with identical DIMMs installed.
Each processor provides four banks of memory, each capable of supporting up to three DIMMs.
 DIMMs are organized into physical slots on DDR3 memory channels that belong to
processor sockets.
 The memory channels from processor socket 1 are identified as Channel A, B, C, and D.
The memory channels from processor socket 2 are identified as Channel E, F, G, and H.
 The silk-screened DIMM slot identifiers on the board provide information about the
channel, and therefore the processor to which they belong. For example, DIMM_A1 is
the first slot on Channel A on processor 1; DIMM_A2 is the second slot on Channel A on
processor 1; DIMM_E1 is the first DIMM socket on Channel E on processor 2; DIMM_E2
is the second DIMM socket on Channel E on processor 2.
 The memory slots associated with a given processor are unavailable if the
corresponding processor socket is not populated.
 A processor may be installed without populating the associated memory slots provided a
second processor is installed with associated memory.
In this case, the memory is
shared by the processors.
However, the platform suffers performance degradation and
latency due to the remote memory.
 Processor sockets are self-contained and autonomous. However, all memory subsystem
support (such as Memory RAS and Error Management) in the BIOS setup is applied
commonly across processor sockets.
Revision 1.6 Intel order number G44057-007 17