Technical Product Specification
Product Architecture Overview Intel
®
Server
Board S2600WP TPS
Non-Transparent Bridge (NTB)
3.3.1
Intel
®
QuickPath Interconnect
The Intel
®
QuickPath Interconnect is a high-speed, packetized, point-to-point interconnect used
in the processor. The narrow high-speed links stitch together processors in distributed shared
memory and integrated I/O platform architecture. It offers much higher bandwidth with low
latency. The Intel
®
QuickPath Interconnect has an efficient architecture allowing more
interconnect performance to be achieved in real systems. It has a snoop protocol optimized for
low latency and high scalability, as well as packet and lane structures enabling quick
completions of transactions. Reliability, availability, and serviceability features (RAS) are built
into the architecture.
The physical connectivity of each interconnect link is made up of 20 differential signal pairs plus
a differential forwarded clock. Each port supports a link pair consisting of two unidirectional links
to complete the connection between two components. This supports traffic in both
directions
simultaneously. To facilitate flexibility and longevity, the interconnect is defined as having five
layers: Physical, Link, Routing, Transport, and Protocol.
The Intel
®
QuickPath Interconnect includes a cache coherency protocol to keep the distributed
memory and caching structures coherent during system operation. It supports both low-latency
source snooping and a scalable home snoop behavior. The coherency protocol provides for
direct cache-to-cache transfers for optimal latency.
3.3.2
Integrated Memory Controller (IMC) and Memory Subsystem
Figure 9. Processor with IMC Functional Block Diagram
Unbuffered or registered DDR3 DIMMs
LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher
capacity memory subsystems
Independent channel mode or lockstep mode
Data burst length of eight cycles for all memory organization modes
QPI
PCIe
IMC -Memory
Controller
Core 0
L1 + L2
Cache
L1 + L2
Cache
L1 + L2
Cache
L1 + L2
Cache
L1 + L2
Cache
L3
Cache
(2.5MB)
0
L3
Cache
(2.5MB)
1
L3
Cache
(2.5MB)
2
L3
Cache
(2.5MB)
3
Core 1
L1 + L2
Cache
Core 2
L1 + L2
Cache
Core 3
L1 + L2
Cache
L3
Cache
(2.5MB)
7
L3
Cache
(2.5MB)
6
L3
Cache
(2.5MB)
5
L3
Cache
(2.5MB)
4
Core 7
Core 6
Core 5
Core 4
Intel order number G44057-007 Revision 1.6
14