Technical Product Specification

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Intel

Server Board S2600WP

Intel order number G44057-007

Revision 1.6

March, 2014

Summary of content (237 pages)

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Intel® Server Board S2600WP Technical Product Specification Intel order number G44057-007 Revision 1.
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Revision History Intel® Server Board S2600WP TPS Revision History Date January 2012 Revision Number 1.0 April 2012 1.1 June 2012 1.2 October 2012 1.3 August 2013 1.4 January 2014 1.5                   March 2014 1.6  Deleted non-ECC statements in 3.3.2 ii Modifications Initial release. Updated storage specification for all block diagrams. Added BMC Core Sensor list. Updated Shock (Unpackaged) data for Server Board Design Specifications.
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Intel® Server Board S2600WP TPS Disclaimers Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Table of Contents Intel® Server Board S2600WP TPS Table of Contents 1. Introduction ........................................................................................................................1 1.1 Section Outline .......................................................................................................1 1.2 Server Board Use Disclaimer .................................................................................2 2. Server Board Overview .......................................
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Intel® Server Board S2600WP TPS Table of Contents 3.5.2 Quad Small Form-factor Pluggable (QSFP) connector ......................................... 35 3.6 Integrated Baseboard Management Controller Overview ..................................... 35 3.6.1 Super I/O Controller .............................................................................................37 3.6.2 Graphics Controller and Video Support ................................................................38 3.6.3 Remote KVM ...........
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Table of Contents Intel® Server Board S2600WP TPS 4.14 Management Engine (ME)....................................................................................62 4.14.1 Overview ..............................................................................................................62 4.14.2 BMC – Management Engine (ME) Distributed Model ........................................... 62 4.14.3 ME System Management Bus (SMBus*) Interface ...............................................63 4.14.
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Intel® Server Board S2600WP TPS Table of Contents 7.10.3 NIC Connectors..................................................................................................159 7.10.4 SATA Connectors ..............................................................................................159 7.10.5 Hard Drive Activity (Input) LED Header .............................................................. 160 7.10.6 Storage Upgrade Key Connector...................................................................
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Table of Contents Intel® Server Board S2600WP TPS 10.2.14 Ripple/Noise .......................................................................................................172 10.2.15 Timing Reuqirement ...........................................................................................172 Appendix A: Integration and Usage Tips ............................................................................ 174 Appendix B: Integrated BMC Sensor Tables..................................................
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Intel® Server Board S2600WP TPS List of Figures List of Figures Figure 1. Intel® Server Board S2600WP (Base SKU) ..................................................................3 Figure 2. Intel® Server Board S2600WPQ/S2600WPF Components ...........................................5 Figure 3. Rear Panel Connector Placement ................................................................................5 Figure 4. Baseboard and Mounting Holes ...............................................................
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List of Figures Intel® Server Board S2600WP TPS Figure 40. System Acoustic and Performance Configuration................................................... 112 Figure 41. Security Screen ......................................................................................................114 Figure 42. Server Management Screen ..................................................................................116 Figure 43. Console Redirection Screen .........................................................
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Intel® Server Board S2600WP TPS List of Tables List of Tables Table 1. Intel® Server Board S2600WP Feature Set ...................................................................3 Table 2. Intel® Server Board S2600WP Features ........................................................................7 Table 3. Mixed Processor Configurations ..................................................................................12 Table 4. Color Definition............................................................
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List of Tables Intel® Server Board S2600WP TPS Table 40. UEFI NIC Configuration ...........................................................................................106 Table 41. Setup Utility – Processor PCIe Link Speed Configuration Screen Fields ................. 107 Table 42. Setup Utility – Processor PCIe Link Speed Configuration Screen Detail Fields ....... 108 Table 43. Setup Utility – Serial Ports Configuration Screen Fields .......................................... 109 Table 44.
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Intel® Server Board S2600WP TPS List of Tables Table 81. Storage Upgrade Key Connector (J6C4) ................................................................. 160 Table 82. Internal 9-pin Serial A (COM1) (J6A2) ..................................................................... 160 Table 83. External USB port Connector (J3A1) ....................................................................... 161 Table 84. Internal USB Connector (J2D1) ...............................................................
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Intel® Server Board S2600WP TPS 1. Introduction Introduction The Intel® Server Board S2600WP is a half-width, dual-socket server board using the Intel® Xeon® Processor E5-2600 and E5-2600 v2 series processor, in combination with Intel® C600-A chipset to provide an outstanding feature set for high-performance and high-density computing.
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Introduction 1.2 Intel® Server Board S2600WP TPS Server Board Use Disclaimer Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components.
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Intel® Server Board S2600WP TPS 2. Server Board Overview Server Board Overview The Intel® Server Board S2600WP is a monolithic printed circuit board (PCB) with features designed to support the high-performance and high-density computing markets. This server board is designed to support the Intel® Xeon® processor E5-2600 and E5-2600 v2 product family. Previous generation Intel® Xeon® processors are not supported. Many of the features and functions of the server board family are common.
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Server Board Overview Feature External I/O Connections Internal I/O connectors/headers Power Connections System Fan Support Add-in Riser Support Video Hard Drive Support RAID Support Server Management 2.1 Intel® Server Board S2600WP TPS      Description DB-15 Video connectors Two RJ-45 Network Interfaces for 10/100/1000 LAN One stacked two-port USB 2.
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Intel® Server Board S2600WP TPS Server Board Overview Description A Description Description 2x7 fan control connector CPU2 DIMM (8 total) I PCH C600-A Q J Riser Slot 4 (PCIe Gen3x16) Riser Slot 3 (PCIe Gen3x16) K E F CPU1 DIMM (8 total) 2x5 USB M N Riser Slot 2 (PCIe Gen3x16) InfiniBand* QDR or FDR InfiniBand* diagnostic and status LED QSFP USB x2 G H IPMB connector Bridge board connector O P Status and ID LED VGA out B C D L Description Y SATA port 1 R Dual port 1GbE NIC chip NIC p
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Server Board Overview 2.1.2 Intel® Server Board S2600WP TPS Server Board Mechanical Drawings The following figure is the mechanical drawing of the Intel® Server Board S2600WP. Figure 4. Baseboard and Mounting Holes 6 Intel order number G44057-007 Revision 1.
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Intel® Server Board S2600WP TPS 3. Product Architecture Overview Product Architecture Overview The Intel® Server Board S2600WP is a purpose-built, rack-optimized server board used in a high-density rack system.
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Product Architecture Overview Intel® Server Board S2600WP TPS ® Figure 5. Intel Server Board S2600WPQ/S2600WPF Functional Block Diagram 8 Intel order number G44057-007 Revision 1.
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Intel® Server Board S2600WP TPS Product Architecture Overview ® Figure 6. Intel Server Board S2600WP Functional Block Diagram 3.2 Processor Support The server board includes two Socket-R (LGA2011) processor sockets and can support Intel® Xeon® processor E5-2600 and E5-2600 v2 product family with a Thermal Design Power (TDP) of up to 135W. The Intel® Xeon® E5-2600 and E5-2600 v2 processor family are composed of 10/12 cores respectively.
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Product Architecture Overview 3.2.1 Intel® Server Board S2600WP TPS Processor Socket Assembly Each processor socket of the server board is pre-assembled with an Independent Latching Mechanism (ILM) and Back Plate that allow for secure placement of the processor and processor heat to the server board. The illustration below identifies each sub-assembly component. Figure 7. Processor Socket Assembly Figure 8. Processor Socket ILM Variations 10 Intel order number G44057-007 Revision 1.
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Intel® Server Board S2600WP TPS Product Architecture Overview The square ILM has an 84x106 mm heatsink mounting hole pattern and is used on the Intel® Server Board S2600WP. Note: The Intel® Server System H2000WP uses two different CPU heatsinks for CPU 1 and CPU 2. FXXCA84X106HS (Cu base-Al fin Heatsink) is for CPU1, and FXXEA84X106HS (Alextruded Heatsink) is for CPU2. Misallocating the heatsinks in Intel® Server System H2000WP will cause serious thermal damage.
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Product Architecture Overview Intel® Server Board S2600WP TPS Table 3. Mixed Processor Configurations Error Processor family not identical Severity Fatal System Action The BIOS detects the error condition and responds as follows:  Logs the error into the system event log (SEL).  Alerts the Integrated BMC of the configuration error with an IPMI command.  Does not disable the processor.  Displays 0194: Processor family mismatch detected message in the error manager.  Halts the system.
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Intel® Server Board S2600WP TPS 3.3 Product Architecture Overview Processor Function Overview With the release of the Intel® Xeon® processor E5-2600 and E5-2600 v2 product family, several key system components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module (IIO), have been combined into a single processor package and feature per socket; two Intel® QuickPath Interconnect point-to-point links capable of up to 8.
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Product Architecture Overview  3.3.1 Intel® Server Board S2600WP TPS Non-Transparent Bridge (NTB) Intel® QuickPath Interconnect The Intel® QuickPath Interconnect is a high-speed, packetized, point-to-point interconnect used in the processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency.
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Intel® Server Board S2600WP TPS Product Architecture Overview  Memory DDR3 data transfer rates of 800, 1066, 1333, 1600, and 1867 MT/s  64-bit wide channels plus 8-bits of ECC support for each channel  DDR3 standard I/O Voltage of 1.5 V for all speeds  DDR3 Low Voltage of 1.
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Product Architecture Overview 3.3.2.1 Intel® Server Board S2600WP TPS Supported Memory Table 4. Color Definition Supported and Validated Supported but not Validated Supported with Limited Validation Table 5. UDIMM Support Guidelines Ranks Per DIMM and Data Width Speed (MT/s) and Voltage Validated by Slot Per Channel (SPC) and DIMM Per Channel (DPC)2,3 Memory Capacity Per DIMM1 2 Slots Per Channel 1DPC SRx8 ECC 1GB 2GB 4GB DRx8 ECC 2GB 4GB 8GB 2DPC 1.35V 1.5V 1.35V 1.
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Intel® Server Board S2600WP TPS Product Architecture Overview Notes: 1. Supported DRAM Densities are 1Gb, 2Gb, and 4Gb. Only 2Gb and 4Gb are validated by Intel. 2. Command Address Timing is 1N. 3. QR RDIMMs are supported but only validated by Intel in a homogenous environment. The coverage will have limited system level testing, no signal integrity testing, and no interoperability testing. The passing QR RDIMMs will be web posted. Table 7.
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Product Architecture Overview Intel® Server Board S2600WP TPS On the Intel® Server Board S2600WP, a total of 16 DIMM slots is provided (two CPUs, four Channels/CPU, and two DIMMs/Channel). The nomenclature for DIMM sockets is detailed in the following table. ® Table 8.
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Intel® Server Board S2600WP TPS Product Architecture Overview  The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term Effective Memory refers to the total size of all DDR3 DIMMs that are active (not disabled) and not used as redundant units.  The BIOS provides the total memory of the system in the main page of the BIOS setup. This total is the same as the amount described by the first bullet above.
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Product Architecture Overview 3.3.2.4.4 Intel® Server Board S2600WP TPS Lockstep Channel Mode In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel 0 and Channel 1, and Channel 2 and Channel 3. Lockstep Channel mode is the only RAS mode that allows SDDC for x8 devices. Lockstep Channel Mode requires that Channel 0 and Channel 1, and Channel 2 and Channel 3 must be populated identically with regards to size and organization.
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Intel® Server Board S2600WP TPS Product Architecture Overview Figure 11. General Functional Block Diagram of Processor I/O Subsystem The following sub-sections describe the server board features that are directly supported by the processor IIO module. These include the Riser Card Slots, Network Interface, and connectors for the optional I/O modules and SAS Module. Features and functions of the Intel® C600-A Series chipset will be described in its own dedicated section. 3.3.3.
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Product Architecture Overview Intel® Server Board S2600WP TPS Figure 12. PCI Express* Lane distribution scheme Table 9.
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Intel® Server Board S2600WP TPS 3.3.3.2 Product Architecture Overview Riser Types The riser slot 1 connector is a standard 164-pin x16 connector. On S2600WP, the riser slot 2 has a x16 PCIe Gen 3 and a x8 PCIe Gen 3 electrical interface in the physical slot. On S2600WPQ and S2600WPF, the riser slot 2 has a x16 PCIe Gen 3 electrical interface. Riser slot 2 connector supports rIOM (Intel® Input/Output Module) mounted on a riser carrier.
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Product Architecture Overview Intel® Server Board S2600WP TPS PCI-E add-in adapters but Intel® rIOM (Intel® Input/Output Module) Carrier. Please refer Intel® server system H2000WP Technical Production Specification for details of rIOM (Intel® Input/Output Module) Carrier.  1U customized Riser for Slot 2 with one PCIe slot – 1 set of x8 signals routed to root port 3A of processor 1 to facilitate Non-Transparent Bridge. Figure 15. PCIe Riser for Slot 2 3.3.3.
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Intel® Server Board S2600WP TPS Product Architecture Overview ® Figure 16. Intel C600-A PCH connection The Intel® C600-A PCH component provides extensive I/O support. Functions and capabilities include:  PCI Express* Base Specification, Revision 2.0 supports up to eight ports with transfers up to 5 GT/s  PCI Local Bus Specification, Revision 2.3 supports 33 MHz PCI operations (supports up to four Req/Gnt pairs)  ACPI Power Management Logic Support, Revision 4.
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Product Architecture Overview Intel® Server Board S2600WP TPS  Supports Intel® Virtualization Technology for Directed I/O (Intel® VT-d)  Supports Intel® Trusted Execution Technology (Intel® TXT)  Low Pin Count (LPC) interface  Firmware Hub (FWH) interface support  Serial Peripheral Interface (SPI) support  Intel® Anti-Theft Technology (Intel® AT)  JTAG Boundary Scan support 3.4.
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Intel® Server Board S2600WP TPS 3.4.3 Product Architecture Overview Universal Serial Bus (USB) There are fourteen USB 2.0 ports available from Intel® C600-A PCH. All ports are high-speed, full-speed and low-speed capable. A total of five USB 2.0 dedicated ports are used by Intel® Server Board S2600WP. The USB port distribution is as follows:  ServerEngines* BMC PILOT III consumes two USB 2.0 ports (one USB1.1 and one USB2.0)  Two rear USB 2.
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Product Architecture Overview Intel® Server Board S2600WP TPS Storage Upgrade Keys. Upgrade keys install onto a four-pin connector on the server board labeled STOR UPG Key. The following table identifies available upgrade key options and their supported features. ® Table 11.
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Intel® Server Board S2600WP TPS 3.4.7 Product Architecture Overview Digital Media Interface (DMI) Digital Media Interface (DMI) is the chip-to-chip connection between the processor and Intel® C600-A PCH. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally. 3.4.
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Product Architecture Overview Intel® Server Board S2600WP TPS security information. The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. 3.4.12 GPIO Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on the Intel® C600-A PCH configuration. 3.4.
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Intel® Server Board S2600WP TPS Product Architecture Overview diagnostic SW or OS installation image and direct the client to boot from IDE-R. The IDE-R interface is the same as the IDE interface and is compliant with ATA/ATAPI-6 specifications. IDE-R does not conflict with the usage of PXE boot. The system can support both interfaces and continue to boot from the PXE as with any other boot devices.
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Product Architecture Overview Intel® Server Board S2600WP TPS The Intel® C600-A PCH’s SMBus* also implements hardware-based Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus* devices. 3.4.20 Network Interface Controller (NIC) Network interface support is provided from the onboard Intel® I350 NIC, which is a dual-port, compact component with two fully integrated GbE Media Access Control (MAC) and Physical Layer (PHY) ports.
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Intel® Server Board S2600WP TPS 3.4.20.1 Product Architecture Overview MAC Address Definition The Intel® Server Board S2600WP has the following four MAC addresses assigned to it at the Intel® factory.
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Product Architecture Overview Intel® Server Board S2600WP TPS Figure 18. ConnectX-3* function block diagram Major features and functions include:      3.5.1 Single InfiniBand* Port: SDR/DDR/QDR on S2600WPQ, SDR/DDR/QDR/FDR on S2600WPF with port remapping in firmware Performance optimization: achieving single port line-rate bandwidth PCI Express* 3.0 x8 to achieve 2.
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Intel® Server Board S2600WP TPS 3.5.2 Product Architecture Overview  I2C Compatible Interfaces: For chip, QSFP connector, and chassis configure, and monitor.  Management Link: Connect to BMC through SMBus* and NC-SI.  Others including: MDIO, GPIO, and JTAG. Quad Small Form-factor Pluggable (QSFP) connector Port of the Mellanox* ConnectX-3* is connected to a single QSFP connector on Intel® Server Board S2600WPQ and S2600WPF.
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Product Architecture Overview Intel® Server Board S2600WP TPS Figure 20. Integrated BMC implementation overview Figure 21. Integrated BMC Functional Block Diagram The Integrated BMC is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI-based server management. Firmware usage of these hardware features is platform dependent.
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Intel® Server Board S2600WP TPS Product Architecture Overview       12 10-bit ADCs Sixteen fan tachometers Eight Pulse Width Modulators (PWM) Chassis intrusion logic JTAG Master Eight I2C interfaces with master-slave and SMBus* timeout support. All interfaces are SMBus* 2.
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Product Architecture Overview 3.6.1.2 Intel® Server Board S2600WP TPS Wake-up Control The super I/O contains a functionality that allows various events to power on and power off the system. 3.6.
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Intel® Server Board S2600WP TPS Product Architecture Overview Table 14. Video mode On-board Video Enabled Disabled Dual Monitor Video Enabled Shaded if on-board video is set to "Disabled" Disabled 3.6.3 Remote KVM The Integrated BMC contains a remote KVMS subsystem with the following features:        Revision 1.6 USB 2.0 interface for keyboard, mouse, and remote storage such as CD/DVD ROM and floppy USB 1.1/USB 2.
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Platform Management Functional Overview 4. Intel® Server Board S2600WP TPS Platform Management Functional Overview Platform management functionality is supported by several hardware and software components integrated on the server board that work together to control system functions, monitor and report system health, and control various thermal and performance features in order to maintain (when possible) server functionality in the event of component failure and/or environmentally stressed conditions.
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Intel® Server Board S2600WP TPS o  4.1.2 Platform Management Functional Overview BMC self-test: The BMC performs initialization and run-time self-tests and makes results available to external entities. See also the Intelligent Platform Management Interface Specification Second Generation v2.0. Non IPMI Features The BMC supports the following non-IPMI features:   In-circuit BMC firmware update.
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Platform Management Functional Overview               Power fault analysis. Intel® Light-Guided Diagnostics. Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported on embedded NICs). Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on embedded NICs). E-mail alerting. Embedded web server. o Support for embedded web server UI in Basic Manageability feature set. o Human-readable SEL. o Additional system configurability.
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Intel® Server Board S2600WP TPS   Embedded platform debug feature which allows capture of detailed data for later analysis. Provisioning and inventory enhancements: o Signed Firmware (improved security). o                       Inventory data/system information export (partial SMBIOS table). Enhancements to fan speed control. DCMI 1.1 compliance (product-specific). Support for embedded web server UI in Basic Manageability feature set. Enhancements to embedded web server.
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Platform Management Functional Overview 4.2 Intel® Server Board S2600WP TPS Advanced Configuration and Power Interface (ACPI) The server board has support for the following ACPI states: Table 15. ACPI Power States State S0 Supported Yes Description Working.  The front panel power LED is on (not controlled by the BMC).  The fans spin at the normal speed, as determined by sensor inputs.  Front panel buttons work normally. S1 Yes Sleeping.
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Intel® Server Board S2600WP TPS Platform Management Functional Overview The BMC acts as master for the other busses connected to it. 4.4 BMC Internal Timestamp Clock The BMC maintains an internal timestamp clock that is used by various BMC subsystems, example for time stamping SEL entries. As part of BMC initialization after AC power is applied or the BMC is reset, the BMC initializes this internal clock to the value retrieved from the SSB component’s RTC through an SMBus* slave read operation.
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Platform Management Functional Overview 4.6.1 Intel® Server Board S2600WP TPS Channel Management Every messaging interface is assigned an IPMI channel ID by IPMI 2.0. Commands are provided to configure each channel for privilege levels and access modes. Table 16 shows the standard channel assignments: Table 16.
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Intel® Server Board S2600WP TPS Platform Management Functional Overview Table 17. Default User Values Users User name Password Status Default Privilege Characteristics Password can be changed. This user may not be used to access the embedded web server. User 1 [Null] [Null] Disabled Admin User 2 root superuser Disabled Admin Password can be changed. User 3 test1 superuser Disabled Admin User name and password can be changed.
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Platform Management Functional Overview Intel® Server Board S2600WP TPS 8. These sessions are not counted as IPMI sessions. (For example, Get Session Info only returns values based on IPMI Sessions). 9. This type of Non-IPMI session can open IPMI sessions as part of a normal operation and those IPMI sessions are counted as IPMI sessions. For example, within a Web Session, one or more IPMI Over LAN Session are ® opened to GetandSet IPMI parameters.
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Intel® Server Board S2600WP TPS Platform Management Functional Overview In addition to the use of an add-in card for a dedicated management channel, on systems that support multiple Ethernet ports on the baseboard, the system BIOS provides a setup option to allow one of these baseboard ports to be dedicated to the BMC for manageability purposes. When this is enabled, that port is hidden from the OS. 4.6.4.
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Platform Management Functional Overview Intel® Server Board S2600WP TPS  An IPv6 address is 16 bytes versus 4 bytes for IPv4.  An IPv6 prefix is 0 to 128 bits whereas IPv4 has a 4 byte subnet mask.  The IPv6 Enable parameter must be set before any IPv6 packets will be sent or received on that channel.  There are two variants of automatic IP Address Source configuration versus just DHCP for IPv4.
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Intel® Server Board S2600WP TPS 4.7 Platform Management Functional Overview System Event Log (SEL) The BMC implements the system event log as specified in the Intelligent Platform Management Interface Specification, Version 2.0. The SEL is accessible regardless of the system power state through the BMC's in-band and out-of-band interfaces. The BMC allocates 65,502 bytes (approximately 64KB) of non-volatile storage space to store system events. The SEL timestamps may not be in order.
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Platform Management Functional Overview 4.8 Intel® Server Board S2600WP TPS Sensor Data Record (SDR) Repository The BMC implements the sensor data record (SDR) repository as specified in the Intelligent Platform Management Interface Specification, Version 2.0. The SDR is accessible through the BMC’s in-band and out-of-band interfaces, regardless of the system power state. The BMC allocates 65,519 bytes of non-volatile storage space for the SDR. 4.
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Intel® Server Board S2600WP TPS Platform Management Functional Overview The following actions cause the BMC to generate an NMI pulse:  Receiving a Chassis Control command to pulse the diagnostic interrupt. This command does not cause an event to be logged in the SEL.  Detecting that the front panel diagnostic interrupt button has been pressed.  Watchdog timer pre-timeout expiration with NMI/diagnostic interrupt pre-timeout action enabled.
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Platform Management Functional Overview Intel® Server Board S2600WP TPS Feature Basic* SMASH CLP Advanced** X X * Basic management features provided by Integrated BMC. ® **Advanced management features available with optional Intel Remote Management Module 4 Lite. ® ***Intel Intelligent Power Node Manager Support requires PMBus*-compliant power supply. 4.12.1 Enabling Advanced Manageability Features The Advanced management features are to be delivered as part of the BMC FW image.
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Intel® Server Board S2600WP TPS Platform Management Functional Overview Other attributes of this feature include:  Encryption of the redirected screen, keyboard, and mouse  Compression of the redirected screen 4.12.1.2 Remote Console The Remote Console is the redirected screen, keyboard, and mouse of the remote host system. To use the Remote Console window of your managed host system, the browser must include a Java* Runtime Environment plug-in.
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Platform Management Functional Overview Intel® Server Board S2600WP TPS The default inactivity timeout is 30 minutes, but may be changed through the embedded web server. Remote KVM activation does not disable the local system keyboard, video, or mouse. Remote KVM is not deactivated by local system input, unless the feature is disabled locally. 4.12.1.7 Usage As the server is powered up, the remote KVM session displays the complete BIOS boot process.
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Intel® Server Board S2600WP TPS Platform Management Functional Overview  It is possible to install an operating system on a bare metal server (no OS present) using the remotely mounted device. This may also require the use of KVM-r to configure the OS during install.  USB storage devices will appear as floppy disks over media redirection. This allows for the installation of device drivers during OS installation.
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Platform Management Functional Overview  Microsoft Internet Explorer 8.0*  Microsoft Internet Explorer 9.0*  Mozilla Firefox 3.0*  Mozilla Firefox 3.5*  Mozilla Firefox 3.6* Intel® Server Board S2600WP TPS The embedded web user interface supports strong security (authentication, encryption, and firewall support) since it enables remote server configuration and control.
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Intel® Server Board S2600WP TPS 4.12.4 Platform Management Functional Overview Data Center Management Interface (DCMI) The DCMI Specification is an emerging standard that is targeted to provide a simplified management interface for Internet Portal Data Center (IPDC) customers. It is expected to become a requirement for server platforms which are targeted for IPDCs. DCMI is an IPMIbased standard that builds upon a set of required IPMI standard commands by adding a set of DCMI-specific IPMI OEM commands.
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Platform Management Functional Overview Intel® Server Board S2600WP TPS CLTT on mixed-mode DIMM populations (that is, some installed DIMMs have valid temp sensors and some do not). The Integrated BMC fan speed control functionality is related to the memory throttling mechanism used. The following terminology is used for the various memory throttling options:  Static Open Loop Thermal Throttling (Static-OLTT): OLTT control registers are configured by BIOS MRC remain fixed after post.
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Intel® Server Board S2600WP TPS 4.12.7.2 Platform Management Functional Overview Type Profile Details CLTT 0 300M altitude CLTT 2 900M altitude CLTT 4 1500M altitude CLTT 6 3000M altitude System Configuration Using FRUSDR Utility The Field Replaceable Unit and Sensor Data Record Update Utility (FRUSDR utility) is a program used to write platform-specific configuration data to NVRAM on the server board.
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Platform Management Functional Overview 4.13.2 Intel® Server Board S2600WP TPS Features NM provides feature support for policy management, monitoring and querying, alerts and notifications, and an external interface protocol. The policy management features implement specific IT goals that can be specified as policy directives for NM. Monitoring and querying features enable tracking of power consumption.
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Intel® Server Board S2600WP TPS Platform Management Functional Overview which may log these into the system SEL and/or output them to the remote application in the form of IPMI LAN alerts. The ServerEngines* Pilot III BMC needs access to various system registers in the processor core silicon and integrated memory controller subsystem. Examples include Processor core and Memory DIMMs temperature information.
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Platform Management Functional Overview 4.14.4 Intel® Server Board S2600WP TPS BMC – Management Engine Interaction Management Engine-Integrated BMC interactions include the following:  Integrated BMC stores sensor data records for ME-owned sensors.  Integrated BMC participates in ME firmware update.   Integrated BMC initializes ME-owned sensors based on SDRs. Integrated BMC receives platform event messages sent by the ME.  Integrated BMC notifies ME of POST completion.
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Intel® Server Board S2600WP TPS  Platform Management Functional Overview Thermal Protection CLST: High power supply thermal event; results in a throttling hiccup mode with fixed maximum throttle time and a fix throttle release ramp time. When the SMBAlert# signal is asserted, the fans will be gated by HW for a short period (~100ms) to reduce overall power consumption.
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BIOS Setup Interface Intel® Server Board S2600WP TPS 5. BIOS Setup Interface 5.1 HotKeys Supported During POST Certain “HotKeys” are recognized during POST. A HotKey a key or key combination that is recognized as an unprompted command input, that is, the operator is not prompted to press the HotKey and typically the HotKey will be recognized even while other processing is in progress. The Intel® Server Board S2600WP Family BIOS recognizes a number of HotKeys during POST.
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Intel® Server Board S2600WP TPS  5.3 BIOS Setup Interface Instructions showing hotkeys for going to Setup, going to popup Boot Menu, starting Network Boot BIOS Boot Pop-up Menu The BIOS Boot Specification (BBS) provides a Boot Pop-up menu that can be invoked by pressing the key during POST. The BBS Pop-up menu displays all available boot devices. The boot order in the pop-up menu is not the same as the boot order in the BIOS setup.
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BIOS Setup Interface 5.4.1.1 Intel® Server Board S2600WP TPS Setup Page Layout The Setup page layout is sectioned into functional areas. Each occupies a specific area of the screen and has dedicated functionality. The following table lists and describes each functional area. The Setup page is designed to a format of 80 x 24 (24 lines of 80 characters each).
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Intel® Server Board S2600WP TPS 5.4.1.2 BIOS Setup Interface Entering BIOS Setup To enter the BIOS Setup using a keyboard (or emulated keyboard), press the function key during boot time when the OEM or Intel® logo is displayed. The following message is displayed on the diagnostics screen and under the Quiet Boot logo screen: Press to enter setup When the Setup Utility is entered, the Main screen is displayed.
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BIOS Setup Interface Key Intel® Server Board S2600WP TPS + Option Change Value Description The plus key on the keypad is used to change the value of the current menu item to the next value. This key scrolls through the values in the associated pick list without displaying the full list. On 106-key Japanese keyboards, the plus key has a different scan code than the plus key on the other keyboards, but will have the same effect.
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Intel® Server Board S2600WP TPS BIOS Setup Interface  The Help Text entry is the actual text which appears on the screen to accompany the item when the item is the one in focus (active on the screen).  The Comments entry provides additional information where it may be helpful. This information does not appear on the BIOS Setup screens. Information enclosed in angular brackets (< >) in the screen shots identifies text that can vary, depending on the option(s) installed.
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BIOS Setup Interface Categories (Top Tabs) Intel® Server Board S2600WP TPS 2nd Level Screens  3rd Level Screens UEFI Option ROM Control Processor PCIe Link Speed  Serial Port Configuration  USB Configuration  System Acoustic and Performance Configuration Security Screen (Tab) Server Management Screen (Tab)  Console Redirection  System Information  BMC LAN Configuration Boot Options Screen (Tab)  Hard Disk Order  Network Device Order  Add EFI Boot Option  Delete EFI Boot Opti
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Intel® Server Board S2600WP TPS 5.4.2.2 BIOS Setup Interface Main Screen (Tab) The Main Screen is the first screen that appears when the BIOS Setup configuration utility is entered, unless an error has occurred. If an error has occurred, the Error Manager Screen appears instead. Main Advanced Security Server Management Boot Options Logged in as: Administrator/User Platform ID Boot Manager System BIOS BIOS Version
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BIOS Setup Interface Setup Item BIOS Version Intel® Server Board S2600WP TPS Options Current BIOS version ID Help Text Comments Information only. The BIOS version displayed uniquely identifies the BIOS that is currently installed and operational on the board. The version information displayed is taken from the BIOS ID String, with the timestamp segment dropped off.
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Intel® Server Board S2600WP TPS Setup Item System Date BIOS Setup Interface Options System Date initially displays the current system calendar date, including the day of the week Help Text System Date has configurable fields for the current Month, Day, and Year. The year must be between 2005 and 2099. Use [Enter] or [Tab] key to select the next field. Comments This field initially displays the current system day of week and date. It may be edited to change the system date.
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BIOS Setup Interface 5.4.2.3 Intel® Server Board S2600WP TPS Advanced Screen (Tab) The Advanced screen provides an access point to configure several groups of options. On this screen, the user can select the option group to be configured. Configuration actions are performed on the selected screen, and not directly on the Advanced screen.
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Intel® Server Board S2600WP TPS Setup Item Serial Port Configuration BIOS Setup Interface Help Text View/Configure serial port information and settings. Comments Selection only. Select this line and press the key to go to the Serial Port Configuration group of configuration settings. USB Configuration View/Configure USB information and settings. Selection only. Select this line and press the key to go to the USB Configuration group of configuration settings.
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BIOS Setup Interface 5.4.2.4 Intel® Server Board S2600WP TPS Processor Configuration The Processor Configuration screen displays the processor identification and microcode level, core frequency, cache sizes, Intel® QuickPath Interconnect information for all processors currently installed. It also allows the user to enable or disable a number of processor options. To access this screen from the Main screen, select Advanced > Processor Configuration.
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Intel® Server Board S2600WP TPS BIOS Setup Interface Advanced Processor Configuration Processor Socket L3 Cache RAM Processor 1 Version Processor 2 Version CPU 1 CPU 2 * | | | | | | Current Intel(R) QPI Link Speed Intel(R) QPI Link Frequency Intel(R) QPI Frequency Select Intel(R) Turbo Boost
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BIOS Setup Interface Intel® Server Board S2600WP TPS Table 30. Setup Utility – Processor Configuration Screen Fields Setup Item Processor ID Options CPUID Help Text Comments Information only. Displays the Processor Signature value (from the CPUID instruction) identifying the type of processor and the stepping. For multi-socket boards, the processor selected as the Bootstrap Processor (BSP) has an asterisk (“*”) displayed beside the Processor ID. “N/A” will be displayed for a processor if not installed.
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Intel® Server Board S2600WP TPS Setup Item L3 Cache RAM BIOS Setup Interface Options L3 cache size Help Text Comments Information only. Displays size in MB of the processor L3 Cache. Because L3 cache is shared between all cores in a processor package, this is shown as the total amount of L3 cache per processor package. The 2-socket boards have a display column for each socket, showing “N/A” for empty sockets where processors are not installed.
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BIOS Setup Interface Setup Item Intel(R) QPI Frequency Select Intel® Server Board S2600WP TPS Options Auto Max 6.4 GT/s 7.2 GT/s 8.0 GT/s Help Text Allows for selecting the ® Intel QuickPath Interconnect Frequency. Recommended to leave in [Auto Max] so that the BIOS can select the ® highest common Intel QuickPath Interconnect frequency. Comments Lowering the QPI frequency may improve performance per watt for some processing loads and on certain benchmarks.
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Intel® Server Board S2600WP TPS Setup Item Intel(R) HyperThreading Tech Options Enabled Disabled BIOS Setup Interface Help Text ® Intel Hyper-Threading Technology allows multithreaded software applications to execute threads in parallel within each processor. Comments This option is only visible if all processors installed in the system ® support Intel Hyper-Threading Technology. Contact your OS vendor regarding OS support of this feature.
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BIOS Setup Interface Setup Item Intel(R) VT for Directed I/O Intel® Server Board S2600WP TPS Options Enabled Disabled Help Text ® Enable/Disable Intel Virtualization Technology ® for Directed I/O (Intel VTd). Report the I/O device assignment to VMM through DMAR ACPI Tables. ® This option only appears when Intel Virtualization Technology for Directed I/O is Enabled. For some processors this will be enabled ® unconditionally whenever Intel VT-d is enabled.
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Intel® Server Board S2600WP TPS Setup Item DCU Data Prefetcher BIOS Setup Interface Options Enabled Disabled Help Text The next cache line will be prefetched into L1 data cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data.
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BIOS Setup Interface 5.4.2.5 Intel® Server Board S2600WP TPS Power and Performance Policy The Power and Performance screen allows the user to specify a profile that is optimized in the direction of either reduced power consumption or increased performance. To access this screen from the Main screen, select Advanced > Power and Performance. To move to another screen, press the key to return to the Advanced screen, then select the desired screen.
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Intel® Server Board S2600WP TPS BIOS Setup Interface Table 32.
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BIOS Setup Interface BIOS Features CKE Throttling Memory Voltage CPU PkgC State Limit Processor C1 mapped to ACPI C1 Processor C6 with retention mapped to ACPI C2 ACPI C3 Processor C1/C3 Auto Demotion Processor C1/C3 UnDemotion ENERGY_PERF _BIAS mode 88 Intel® Server Board S2600WP TPS Available Settings Performance Balanced Performance (Auto) Balanced Power Power (Auto) Enabled 1.
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Intel® Server Board S2600WP TPS 5.4.2.6 BIOS Setup Interface Memory Configuration The Memory Configuration screen allows the user to view details about the DDR3 DIMMs that are installed as system memory. To access this screen from the Main screen, select Advanced > Memory Configuration. To move to another screen, press the key to return to the Advanced screen, then select the desired screen.
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BIOS Setup Interface Intel® Server Board S2600WP TPS Table 33. Setup Utility – Memory Configuration Screen Fields Setup Item Total Memory Options Effective Memory Help Text Comments Information only. Displays the amount of memory available in the system in the form of installed DDR3 DIMMs, in units of GB. Information only. Displays the amount of memory available to the OS in MB or GB.
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Intel® Server Board S2600WP TPS Setup Item Phase Shedding BIOS Setup Interface Options Enabled Disabled Help Text Enable/disable DDR3 VR Static Phase Shedding. When enabled, DDR3 VR can be automatically adjusted by typical load. Comments This feature helps DDR3 VR optimize for high loading.
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BIOS Setup Interface Setup Item DIMM_A1 DIMM_A2 DIMM_B1 DIMM_B2 DIMM_C1 DIMM_C2 DIMM_D1 DIMM_D2 DIMM_E1 DIMM_E2 DIMM_F1 DIMM_F2 DIMM_G1 DIMM_G2 DIMM_H1 DIMM_H2 Intel® Server Board S2600WP TPS Options Help Text Where DIMM Size: Size of DIMM in GB DIMM Status: Installed&Operational, Not Installed, Failed/Disabled Comments Information only. Displays the status of each DIMM socket present on the board. There is one line for each DIMM socket present on the board.
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Intel® Server Board S2600WP TPS 5.4.2.7 BIOS Setup Interface Memory RAS and Performance Configuration The Memory RAS and Performance Configuration screen allows the user to customize several memory configuration options, such as whether to use Memory Mirroring or Memory Sparing. To access this screen from the Main screen, select Advanced > Memory Configuration > Memory RAS and Performance Configuration.
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BIOS Setup Interface Setup Item NUMA Optimized Intel® Server Board S2600WP TPS Options Enabled Disabled 94 Help Text If enabled, the BIOS includes ACPI tables that are required for NUMAaware Operating Systems. Intel order number G44057-007 Comments This option is only present for boards that have two or more processor sockets. When a multi-socket board has only a single processor installed, this option is grayed out and set as Disabled. Revision 1.
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Intel® Server Board S2600WP TPS 5.4.2.8 BIOS Setup Interface Mass Storage Controller Configuration The Mass Storage Configuration screen allows the user to configure the Mass Storage controllers that are integrated into the server board on which the BIOS is executing. This includes only onboard Mass Storage controllers. Mass Storage controllers on add-in cards are not included in this screen, nor are other storage mechanisms such as USB-attached storage devices or Network Attached Storage.
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BIOS Setup Interface Intel® Server Board S2600WP TPS Table 35. Setup Utility – Mass Storage Controller Configuration Fields Setup Item AHCI Controller Configuration Options Help Text SATA/SAS Controller Configuration AHCI Capable SATA Controller Information only. Disabled - Compatibility Enhanced - AHCI - RAID Mode - This option configures the onboard AHCI-capable SATA controller, which is distinct from the SCU. This option selects the target HDDs that will spin up at system boot.
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Intel® Server Board S2600WP TPS Setup Item SATA Port BIOS Setup Interface Options Not Installed Help Text Drive Information Comments Information only. The Drive Information, when present, will typically consist of the drive model identification and size for the disk drive installed on a particular port. This Drive Information line is repeated for all six SATA ports for the onboard AHCI capable SATA Controller.
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BIOS Setup Interface 5.4.2.9 Intel® Server Board S2600WP TPS PCI Configuration The PCI Configuration screen allows the user to configure the PCI memory space used for onboard and add-in adapters, configure video options, and configure onboard adapter options. It also includes selection options to go to the NIC Configuration screen and Processor PCIe Link Speed screen. To access this screen from the Main screen, select Advanced > PCI Configuration.
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Intel® Server Board S2600WP TPS Setup Item Memory Mapped I/O above 4GB Options Enabled BIOS Setup Interface Disabled Help Text Enable or disable memory mapped I/O of 64-bit PCI devices to 4 GB or greater address space. Comments When enabled, PCI/PCIe Memory Mapped I/O for devices capable of 64bit addressing is allocated to address space above 4GB, in order to allow larger allocations and avoid impacting address space below 4GB.
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BIOS Setup Interface Setup Item Processor PCIe Link Speed 100 Intel® Server Board S2600WP TPS Options Help Text View/Configure Processor PCIe Link Speed. Intel order number G44057-007 Comments Selection only. Select this line and press the key to go to the Processor PCIe Link Speed Configuration group of configuration settings. Revision 1.
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Intel® Server Board S2600WP TPS 5.4.2.10 BIOS Setup Interface NIC Configuration The NIC Configuration screen allows the user to configure on board NIC port 1 and port 2.
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BIOS Setup Interface Setup Item PXE 1GbE Option ROM Intel® Server Board S2600WP TPS Options Enabled Disabled Help Text Enable/Disable Onboard/IOM NIC PXE Option ROM Load. Comments This selection is to enable/disable the 1GbE PXE Option ROM that is used by all Onboard and IO Module 1GbE controllers. This option is grayed out and not accessible if the discs Option ROM is enabled. It can co-exist with the 10GbE PXE Option ROM, the 10GbE FCoE Option ROM, or with an InfiniBand* controller Option ROM.
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Intel® Server Board S2600WP TPS Setup Item NIC1 Controller Options Enable Disable BIOS Setup Interface Help Text Enable/Disable Onboard Network Controller. Comments This will completely disable Onboard Network Controller NIC1 or NIC2, along with all included NIC Ports and their associated options. That controller’s NIC Ports, Port PXE options, and Port MAC Address displays will not appear. This option only appears for onboard Ethernet controllers. It does not appear for onboard InfiniBand* controllers.
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BIOS Setup Interface 5.4.2.11 Intel® Server Board S2600WP TPS UEFI Network Stack The UEFI Network Stack provides access to network devices while executing in the UEFI boot services environment. This screen allows the user to configure UEFI Network Stack Settings. UEFI Network Stack UEFI Network Stack Enabled/Disabled IPv4 PXE Support Enabled/Disabled Figure 32. UEFI Network Stack Configuration Screen Table 38.
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Intel® Server Board S2600WP TPS 5.4.2.12 BIOS Setup Interface UEFI Option ROM Control This screen allows the user to configure UEFI Option ROM Settings. UEFI Option ROM Control UEFI Option ROM Control Intel® I350 Gigabit Network Connection – xx:xx:xx:xx:xx:xx Intel® I350 Gigabit Network Connection – xx:xx:xx:xx:xx:xx Figure 33. UEFI Option ROM Configuration Screen Table 39.
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BIOS Setup Interface 5.4.2.13 Intel® Server Board S2600WP TPS i350 Gigabit Network Connection This screen allows the user to configure LOM NIC settings. Intel® I350 Gigabit Network Connection - xx:xx:xx:xx:xx:xx PORT CONFIGURATION MENU ► NIC Configuration Blink LEDs (Range 0-15 seconds) 0 PORT CONFIGURATION INFORMATION UEFI Driver: Intel® 1GbE DEV x.x.
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Intel® Server Board S2600WP TPS 5.4.2.14 BIOS Setup Interface Processor PCIe Link Speed Configuration The Processor PCIe Link Speed configuration screen allows the user to configure the PCIe Link Speed of the Processor IIO PCIe root port and the PCIe devices connected to this port. To access this screen from the Main screen, select Advanced > PCI Configuration > Processor PCIe Link Speed.
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BIOS Setup Interface Intel® Server Board S2600WP TPS Socket 2 PCIe Ports Link Speed Socket 2, PCIe Port 2a Gen3 (8GT/s) / Gen2 (5GT/s) / Gen1 (2.5GT/s) Socket 2, PCIe Port 3a Gen3 (8GT/s) / Gen2 (5GT/s) / Gen1 (2.5GT/s) Figure 37. CPU 2 PCIe Link Speed Configuration in Detail Table 42. Setup Utility – Processor PCIe Link Speed Configuration Screen Detail Fields Setup Item Socket X, DMI Options Gen2 (5GT/s) Help Text Comments DMI link speed selection. Gen1 (2.
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Intel® Server Board S2600WP TPS 5.4.2.15 BIOS Setup Interface Serial Port Configuration The Serial Port Configuration screen allows the user to configure the Serial A [COM 1] and Serial B [COM2] ports. To access this screen from the Main screen, select Advanced > Serial Port Configuration. To move to another screen, press the key to return to the Advanced screen, then select the desired screen.
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BIOS Setup Interface 5.4.2.16 Intel® Server Board S2600WP TPS USB Configuration The USB Configuration screen allows the user to configure the USB controller options. To access this screen from the Main screen, select Advanced > USB Configuration. To move to another screen, press the key to return to the Advanced screen, then select the desired screen.
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Intel® Server Board S2600WP TPS Setup Item Port 60/64 Emulation Options Enabled Disabled BIOS Setup Interface Help Text Enables I/O port 60h/64h emulation support. Note: This may be needed for legacy USB keyboard support when using an OS that is USB unaware. Make USB Devices NonBootable Enabled Exclude USB in Boot Table. Disabled [Enabled] – This removes all USB Mass Storage devices as Boot options. [Disabled] – This allows all USB Mass Storage devices as Boot options.
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BIOS Setup Interface 5.4.2.17 Intel® Server Board S2600WP TPS System Acoustic and Performance Configuration The System Acoustic and Performance Configuration screen allows the user to configure the thermal control behavior of the system with respect to what parameters are used in the system’s Fan Speed Control algorithms. To access this screen from the Main screen, select Advanced > System Acoustic and Performance Configuration.
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Intel® Server Board S2600WP TPS Setup Item Altitude Options 300m or less 301m-900m 901m-1500m Higher than 1500m BIOS Setup Interface Help Text [300m or less] (980ft or less) – Optimal performance setting near sea level [301m-900m] (980ft-2950ft) – Optimal performance setting at moderate elevation Comments This option sets an altitude value in order to choose a Fan Profile that is optimized for the air density at the current altitude at which the system is installed.
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BIOS Setup Interface 5.4.2.18 Intel® Server Board S2600WP TPS Security Screen (Tab) The Security screen allows the user to enable and set the user and administrative password and to lock out the front panel buttons so they cannot be used. This screen also allows the user to enable and activate the Trusted Platform Module (TPM) security settings on those boards that support TPM.
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Intel® Server Board S2600WP TPS Setup Item Set User Password Options Entry Field – 0-14 characters BIOS Setup Interface Help Text User password is used if Power On Password is enabled and to allow restricted access to BIOS Setup. Length is 1-14 characters. Case sensitive alphabetic, numeric and special characters !@#$%^&*()_+=? are allowed. Note: Removing the administrator password also removes the user password. Power ON Password Enabled Disabled Enable Power On Password support.
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BIOS Setup Interface 5.4.2.19 Intel® Server Board S2600WP TPS Server Management Screen (Tab) The Server Management screen allows the user to configure several server management features. This screen also provides an access point to the screens for configuring console redirection, displaying system information, and controlling the BMC LAN configuration.
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Intel® Server Board S2600WP TPS BIOS Setup Interface Table 47. Setup Utility – Server Management Configuration Screen Fields Setup Item Assert NMI on SERR Options Enabled Disabled Help Text On SERR, generate an NMI and log an error. Note: Enabled must be selected for the Assert NMI on PERR setup option to be visible. Assert NMI on PERR Enabled Disabled On PERR, generate an NMI and log an error. Note: This option is only active if the Assert NMI on SERR option is Enabled selected.
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BIOS Setup Interface Setup Item FRB-2 Enable Options Enabled Disabled OS Boot Watchdog Timer OS Boot Watchdog Timer Policy Enabled Disabled Power Off Reset Intel® Server Board S2600WP TPS Help Text Fault Resilient Boot (FRB). Comments This option controls whether the system will be reset if the BMC Watchdog The BIOS programs the BMC watchdog timer for approximately six Timer detects what appears to be a hang during POST. When the BMC minutes.
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Intel® Server Board S2600WP TPS 5.4.2.20 BIOS Setup Interface Console Redirection The Console Redirection screen allows the user to enable or disable Console Redirection for Remote Management, and to configure the connection options for this feature. To access this screen from the Main screen, select Server Management > Console Redirection. To move to another screen, press the key to return to the Server Management screen, then select the desired screen.
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BIOS Setup Interface Setup Item Terminal Type Options PC-ANSI VT100 VT100+ Intel® Server Board S2600WP TPS Help Text Character formatting used for console redirection. This setting must match the remote terminal application. Comments The VT100 and VT100+ terminal emulations are essentially the same. VTUTF8 is a UTF8 encoding of VT100+. PCANSI is the native character encoding used by PC-compatible applications and emulators. This option enables legacy OS redirection (i.e., DOS) on serial port.
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Intel® Server Board S2600WP TPS 5.4.2.21 BIOS Setup Interface System Information The System Information screen allows the user to view part numbers, serial numbers, and firmware revisions. This is an Information Only screen To access this screen from the Main screen, select Server Management > System Information. To move to another screen, press the key to return to the Server Management screen, then select the desired screen.
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BIOS Setup Interface 5.4.2.22 Intel® Server Board S2600WP TPS BMC LAN Configuration The BMC configuration screen allows the Setup user to configure the BMC Baseboard LAN channel and the RMM4 LAN channel, and to manage BMC User settings for up to five BMC Users. To access this screen from the Main screen, select Server Management > System Information. To move to another screen, press the key to return to the Server Management screen, then select the desired screen.
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Intel® Server Board S2600WP TPS BIOS Setup Interface Server Management BMC LAN Configuration Baseboard LAN configuration IP Source IP Address Subnet Mask Gateway IP Baseboard LAN IPv6 configuration IPv6 IPv6 source IPv6 address Gateway IPv6 IPv6 Prefix Length Intel® RMM4 LAN configuration Intel® RMM4 IP Source IP Address Subnet Mask Gateway IP Intel® RMM4 LAN IPv6 configuration IPv6 Source IPv6 Address Static/Dynamic [0.0.0.0] [0.0.0.0] [0.0.0.0] Disable/Enable Static/Dynamic/Auto [0000.0000.0000.0000.
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BIOS Setup Interface Intel® Server Board S2600WP TPS Table 50. Setup Utility – BMC Configuration Screen Fields Setup Item IP source Options Help Text Static Select BMC IP Source: If [Static], IP parameters may be edited. If [Dynamic], these fields are display-only and IP address is acquired automatically (DHCP). Dynamic IP address View/Edit IP address. Press to edit. Subnet Mask View/Edit subnet address. Press to edit. Gateway IP View Edit Gateway IP address.
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Intel® Server Board S2600WP TPS Setup Item Options BIOS Setup Interface Help Text Comments User Name Press to edit user name. User name is a string of 4 to 15 alphanumeric characters , and must begin with an alphabetic character. User Name cannot be changed for User1 (anonymous) and User2 (root). User Name can only be edited for users other than “anonymous” and “root”. Those two User Names may not be changed. User Password Press key to enter password.
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BIOS Setup Interface 5.4.2.23 Intel® Server Board S2600WP TPS Boot Options Screen (Tab) The Boot Options screen displays all bootable media encountered during POST, and allows the user to configure the desired order in which boot devices are to be tried.
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Intel® Server Board S2600WP TPS BIOS Setup Interface Table 51. Setup Utility – Boot Options Screen Fields Setup Item System Boot Timeout Options 0-65535 Help Text The number of seconds the BIOS will pause at the end of POST to allow the user to press the [F2] key for entering the BIOS Setup utility. Comments After entering the desired timeout, press the key to register that timeout value to the system. These settings are in seconds. The timeout value entered will take effect on the next boot.
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BIOS Setup Interface Setup Item Static Boot Ordering Intel® Server Board S2600WP TPS Options Enabled Disabled Help Text [Disabled] – Devices removed from the system are deleted from Boot Order Tables. [Enabled] – Devices removed have positions in Boot Order Tables retained for later reinsertion. Comments When the option changes to “Enabled” from “Disabled”, it will enable Static Boot Ordering (SBO) from the next boot onward, and also the current Boot Order will be stored as the SBO template.
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Intel® Server Board S2600WP TPS 5.4.2.24 BIOS Setup Interface Hard Disk Order The Hard Disk Order screen allows the user to control the order in which BIOS attempts to boot from the hard disk drives installed in the system. This screen is only available when there is at least one hard disk device available in the system configuration. Note that a USB attached Hard Disk drive or a USB Key device formatted as a hard disk will appear in this section.
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BIOS Setup Interface 5.4.2.25 Intel® Server Board S2600WP TPS Network Device Order The Network Device Order screen allows the user to control the order in which BIOS attempts to boot from the network bootable devices installed in the system. This screen is only available when there is at least one network bootable device available in the system configuration. To access this screen from the Main screen, select Boot Options > Network Device Order.
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Intel® Server Board S2600WP TPS 5.4.2.26 BIOS Setup Interface Add EFI Boot Option The Add EFI Boot Option screen allows the user to add an EFI boot option to the boot order. This screen is only available when there is at least one EFI bootable device present in the system configuration. The “Internal EFI Shell” Boot Option is permanent and cannot be added or deleted. To access this screen from the Main screen, select Boot Options > Add EFI Boot Option.
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BIOS Setup Interface 5.4.2.27 Intel® Server Board S2600WP TPS Delete EFI Boot Option The Delete EFI Boot Option screen allows the user to remove an EFI boot option from the boot order. The “Internal EFI Shell” Boot Option will not be listed, because it is permanent and cannot be added or deleted. To access this screen from the Main screen, select Boot Options > Delete EFI Boot Option. To move to another screen, press the key to return to the Boot Options screen, then select the desired screen.
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Intel® Server Board S2600WP TPS 5.4.2.28 BIOS Setup Interface Boot Manager Screen (Tab) The Boot Manager screen allows the user to view a list of devices available for booting, and to select a boot device for immediately booting the system. Note that this list is not in order according to the system Boot Option order. The “Internal EFI Shell” will always be available, regardless of whether any other bootable devices are available.
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BIOS Setup Interface 5.4.2.29 Intel® Server Board S2600WP TPS Error Manager Screen (Tab) The Error Manager screen displays any POST Error Codes encountered during BIOS POST, along with an explanation of the meaning of the Error Code in the form of a Help Text. This is an Information Only screen. To access this screen from the Main screen or other top-level “Tab” screen, press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Error Manager screen is selected.
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Intel® Server Board S2600WP TPS 5.4.2.30 BIOS Setup Interface Save and Exit Screen (Tab) The Exit screen allows the user to choose whether to save or discard the configuration changes made on other Setup screens. It also allows the user to restore the BIOS settings to the factory defaults or to save or restore them to a set of user-defined default values. If “Load Default Values” is selected, the factory default settings (noted in bold in the Setup screen images) are applied.
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BIOS Setup Interface Setup Item Save as User Default Values Intel® Server Board S2600WP TPS Help Text Save current BIOS Setup utility values as custom user default values. If needed, the user default values can be restored through the “Load User Default Values” option below. Comments User prompted for confirmation. Note: Clearing the CMOS or NVRAM does not cause the User Default values to be reset to the factory default values.
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Intel® Server Board S2600WP TPS 5.5 BIOS Setup Interface Loading BIOS Defaults Different mechanisms exist for resetting the system configuration to the default values. When a request to reset the system configuration is detected, the BIOS loads the default system configuration values during the next POST. You can send the request to reset the system to the defaults in the following ways:  Pressing from within the BIOS Setup utility.   Moving the clear system configuration jumper.
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Configuration Jumpers 6. Intel® Server Board S2600WP TPS Configuration Jumpers The following table provides a summary and description of configuration, test, and debug jumpers on the Intel® Server Board S2600WP. The server board has several three-pin jumper blocks that can be used. Pin 1 on each jumper block can be identified by the following symbol on the silkscreen: Figure 54. Jumper Blocks (J6B1, J1E2, J1E3, J1E1, J1D5) Table 59.
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Intel® Server Board S2600WP TPS Jumper Name J1E3: Password Clear Configuration Jumpers Jumper Position 1-2 Mode of Operation Normal Note Normal mode, password in protection 2-3 Clear Password BIOS password is cleared J1E1: BIOS Recovery Mode 1-2 Normal Normal mode 2-3 Recovery BIOS in recovery mode J1D5: BIOS Default 1-2 Normal Normal mode 2-3 Clear BIOS Settings BIOS settings are reset to factory default 6.
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Configuration Jumpers Intel® Server Board S2600WP TPS fails. This jumper should remain in the default/disabled position when the server is running normally. The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. 6.2 Force ME Update (J1E2) When this 3-pin jumper is set, it manually puts the ME firmware in update mode, which enables the user to update ME firmware code when necessary. Table 61.
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Intel® Server Board S2600WP TPS Configuration Jumpers Table 62. Password Clear Jumper Jumper Position 1-2 Mode of Operation Normal Note Normal mode, password in protection 2-3 Clear Password BIOS password is cleared Steps to clear the BIOS password: 1. Power down server. Do not unplug the power cord. 2. Open the chassis. For instructions, see your server chassis documentation. 3.
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Configuration Jumpers Intel® Server Board S2600WP TPS After the update is complete, a message displays, stating the “BIOS has been updated successfully”. This indicates the recovery process is finished. The user should then switch the recovery jumper back to normal operation and restart the system by performing a power cycle. The following steps demonstrate this recovery process: 1. Power OFF the system. 2. Insert recovery media. 3. Switch the recovery jumper.
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Intel® Server Board S2600WP TPS Configuration Jumpers Note: Removing AC Power before performing the BIOS settings Clear operation causes the system to automatically power up and immediately power down, after the procedure is followed and AC power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds, and re-install the AC power cord. Power-up the system and proceed to the BIOS Setup Utility to reset the desired settings. Revision 1.
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Connector/Header Locations and Pin-out Intel® Server Board S2600WP TPS 7. Connector/Header Locations and Pin-out 7.1 Power Connectors To facilitate customers who want to cable to this board from a power supply, the power connector is implemented through two 6-pin Minifit Jr* connectors, that can be used to deliver 12amps per pin or 60+Amps total. Note that no over-voltage protective circuits will exist on the board. Table 65.
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Intel® Server Board S2600WP TPS Connector/Header Locations and Pin-out A 2x40 pin card edge connector (to backplane) B USB 2.0 Type-A connector C 2-pin 5V_AUX power D AHCI SATA0 DOM port connector E 2x40 pin card edge connector (to baseboard slot) Figure 55. Connectors on Bridge Board Table 68.
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Connector/Header Locations and Pin-out Side Even Intel® Server Board S2600WP TPS 34 Signal FP RST BTN_N Side Odd 33 GND Signal 32 FP ID BTN_N 31 SMB_HSBP_3V3STBY_CLK 30 FP ID LED_N 29 SMB_HSBP_3V3STBY_DATA 28 FP PWR LED_N 27 GND 26 FP STS LED G_N 25 SMB_3V3STBY_CLK 24 FP STS LED A_N 23 SMB_3V3STBY_DATA 22 FP ACT LED_N 21 GND 20 FP HDD ACT LED_N 19 IPMB-5VSTBY_Clk 18 GND 17 IPMB-5VSTBY_Data 16 USB2_P0_DN 15 GND 14 USB2_P0_DP 13 SPARE 12 GND 11 ALL_NODE_OFF
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Intel® Server Board S2600WP TPS Connector/Header Locations and Pin-out sleep state into which the system transitions, if any. Otherwise, the BIOS turns off the system. 7.5 Reset Button The platform supports a front control panel reset button. Pressing the reset button initiates a request forwarded by the Integrated BMC to the chipset. The BIOS does not affect the behavior of the reset button. 7.6 Chassis Identify Button The front panel Chassis Identify button toggles the state of the chassis ID LED.
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Connector/Header Locations and Pin-out Intel® Server Board S2600WP TPS Figure 56. System Status LED (A) and ID LED (B) Table 70. System Status LED Color Green State Solid on System Status OK System ready Description Green ~1 Hz blink Degraded BIOS detected Unable to use all of the installed memory 1 (more than one DIMM installed). In a mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not covered by 1 (2). PCI Express* correctable link errors.
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Intel® Server Board S2600WP TPS Color Amber State ~1 Hz blink Connector/Header Locations and Pin-out System Status Non-Fatal Description Non-fatal alarm – system is likely to fail: BIOS Detected In non-mirroring mode, if the threshold of ten correctable errors is crossed within the 1 window. PCI Express* uncorrectable link errors. Integrated BMC Detected. Critical threshold crossed – Voltage, temperature, power nozzle, power gauge, and PROCHOT (therm Ctrl) sensors. VRD Hot asserted.
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Connector/Header Locations and Pin-out Intel® Server Board S2600WP TPS State Identify active through command LED State ~1 Hz blink Off Off There is no precedence or lock-out mechanism for the control sources. When a new request arrives, all previous requests are terminated. For example, if the chassis ID LED is blinking and the chassis ID button is pressed, then the chassis ID LED changes to solid on. If the button is pressed again with no intervening commands, the chassis ID LED turns off. 7.
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Intel® Server Board S2600WP TPS Pin B17 Pin Name GND Pin A17 Pin Name REFCLK+ Description Clock pair 1 B18 PETxP0 Tx Lane 0+ A18 REFCLK- Clock pair 1 B19 PETxN0 Tx Lane 0- A19 GND B20 B21 GND A20 PERxP0 Rx Lane 0+ GND A21 PERxN0 Rx Lane 0- B22 PETxP1 Tx Lane 1+ A22 GND B23 PETxN1 B24 GND Tx Lane 1- A23 GND A24 PERxP1 Rx Lane 1+ B25 GND B26 PETxP2 Tx Lane 2+ A25 PERxN1 Rx Lane 1- A26 GND B27 PETxN2 Tx Lane 2- A27 GND B28 B29 GND A28 PERxP2 Rx Lane 2+
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Connector/Header Locations and Pin-out Pin Pin Name 0 Intel® Server Board S2600WP TPS Description Pin Pin Name Description B60 GND A60 PERxP10 Rx Lane 10+ B61 GND A61 PERxN10 Rx Lane 10- B62 PETxP1 1 Tx Lane 11+ A62 GND B63 PETxN1 1 Tx Lane 11- A63 GND B64 GND A64 PERxP11 Rx Lane 11+ B65 GND A65 PERxN11 Rx Lane 11- B66 PETxP1 2 Tx Lane 12+ A66 GND B67 PETxN1 2 Tx Lane 12- A67 GND B68 GND A68 PERxP12 Rx Lane 12+ B69 GND A69 PERxN12 Rx Lane 12- B70 PET
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Intel® Server Board S2600WP TPS Side Even 188 Signal Connector/Header Locations and Pin-out Side Odd Description GND Signal 187 5VAUX Description temp sensor For DNM and IOM wake on LAN 185 PRESENT# rIOM (Intel Input/Output Module) function present 183 181 179 177 175 173 171 169 167 165 163 161 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 107 105 103 101 99 97 95 93 RIOM_ACT# RXD_3 RXD_2 RXD_1 RXD_0 GND RX_CTL GND RX_CLK MDC GND IB_CL
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Connector/Header Locations and Pin-out Side Even 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 Signal IB_T01GND IB_T02+ IB_T02GND IB_T03+ IB_T03GND IB_T04+ IB_T04GND IB_T05+ IB_T05GND GND GND IB_T06+ IB_T06GND IB_T07+ IB_T07GND T08+ T08GND T09+ T09GND T10+ T10GND T11+ T11GND T12+ T12GND T13+ T13GND T14+ T14GND T15+ T15GND Intel® Server Board S2600WP TPS Side Odd 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55
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Intel® Server Board S2600WP TPS Revision 1.6 Connector/Header Locations and Pin-out Side even 118 Signal 12V Side Odd 117 Signal SMBUS* 116 12V 115 GND 114 3.
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Connector/Header Locations and Pin-out 156 Intel® Server Board S2600WP TPS Side even 32 Signal GND Side Odd 31 Signal R11+ 30 T11+ 29 R11- 28 T11- 27 GND 26 GND 25 R12+ 24 T12+ 23 R12- 22 T12- 21 GND 20 GND 19 R13+ 18 T13+ 17 R13- 16 T13- 15 GND 14 GND 13 R14+ 12 T14+ 11 R14- 10 T14- 9 GND 8 GND 7 R15+ 6 T15+ 5 R15- 4 T15- 3 GND 2 GND 1 Riser ID Intel order number G44057-007 Revision 1.
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Intel® Server Board S2600WP TPS Connector/Header Locations and Pin-out Table 75. PCI Express* x16 Riser Slot 4 Connector (J1H1) Pin Revision 1.6 PCIe Description MA1 Pin Description B1 SMCLK B2 3.3VAUX B3 GND B4 REFCLK+ Clock pair 2 A4 REFCLK+ Clock pair 1 B5 REFCLK- Clock pair 2 A5 REFCLK- Clock pair 1 B6 GND NA6 GND N B7 PERST# EA7 ID I B8 WAKE# AA8 8KE For wake on LAN NA3 SMDATA Riser A2 GND B9 A9 B10 A10 B11 A11 B12 GND B13 B14 B15 GND B16 M 3.
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Connector/Header Locations and Pin-out Pin PCIe Intel® Server Board S2600WP TPS Description Pin Riser Description B40 PETxP9 Tx Lane 9+ A40 PERxP9 Rx Lane 9+ B41 PETxN9 Tx Lane 9- A41 PERxN9 Rx Lane 9- B42 GND NA42 GND B43 PETxP10 Tx Lane 10+ A43 PERxP10 Rx Lane 10+ B44 PETxN10 Tx Lane 10- A44 PERxN10 Rx Lane 10- B45 GND B46 PETxP11 Tx Lane 11+ A46 PERxP11 Rx Lane 11+ B47 PETxN11 Tx Lane 11- A47 PERxN11 Rx Lane 11- B48 GND B49 PETxP12 Tx Lane 12+ A49 PE
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Intel® Server Board S2600WP TPS Pin 7.10.
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Connector/Header Locations and Pin-out Intel® Server Board S2600WP TPS Table 79. SATA Connector Pin 1 2 3 4 5 6 7 Signal Name GND SATA_TX_P SATA_TX_N GND SATA_RX_N SATA_RX_P P5V_SATA/GND Description Ground Positive side of transmit differential pair Negative side of transmit differential pair Ground Negative side of receive differential pair Positive side of receive differential pair +5V for DOM or Ground for SATA signals Note: SATA DOM requires external power cannot be used with SATA-1 port. 7.10.
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Intel® Server Board S2600WP TPS 7.10.8 Connector/Header Locations and Pin-out USB Connectors The following table details the pin-out of the external stack USB port 0/1 connectors (J3A1) found on the back edge of the server board. Table 83.
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Connector/Header Locations and Pin-out Side A 19 Intel® Server Board S2600WP TPS Signal Side B GND 19 Signal GND 7.11 Fan Headers To facilitate the connection of 3 x40mm double rotor fans, a 14 pin header is provided, all fans will share a PWM. Both rotor tachs can be monitored. Table 86.
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Intel® Server Board S2600WP TPS 8. Intel® Light-Guided Diagnostics Intel® Light-Guided Diagnostics Intel® Server Board S2600WP has several onboard diagnostic LEDs to assist in troubleshooting board-level issues. This section provides a description the location and function of each LED on the server board. 8.1 Front Panel Support The Intel® Server Board S2600WP supports Mini-FP on Intel® Server Chassis H2000WP. The front panel control signals are provided through bridge board.
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Intel® Light-Guided Diagnostics Intel® Server Board S2600WP TPS Table 88. Network link/activity LED LED LAN – Link/Activity 8.1.4 Color Condition Green Green On Blink Off What It Means LAN link/no access LAN access Idle Dedicated InfiniBand* Link/Activity LED The server board provides dedicated LEDs for InfiniBand* Link/Activity. They are located on the baseboard rear, near diagnostic LED set. This set of LEDs only works on S2600WPQ baseboard. See block B in Figure 57 for the location of LEDs.
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Intel® Server Board S2600WP TPS Intel® Light-Guided Diagnostics Figure 57. Rear Panel Diagnostic LEDs (Block A) Revision 1.
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Environmental Limits Specification 9. Intel® Server Board S2600WP TPS Environmental Limits Specification Operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect long term system reliability. Table 90.
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Intel® Server Board S2600WP TPS 9.1.1 Environmental Limits Specification Set Throttling Mode This option is used to select the desired memory thermal throttling mechanism. Available settings include:     [Auto] – Factory Default Setting - BIOS automatically detects and identifies the appropriate thermal throttling mechanism based on DIMM type, airflow input, and DIMM sensor availability.
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Environmental Limits Specification 9.1.6 Intel® Server Board S2600WP TPS Thermal Sensor Input for Fan Speed Control The BMC uses various IPMI sensors as inputs to fan speed control. Some of the sensors are actual physical sensors and some are “virtual” sensors derived from calculations.
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Intel® Server Board S2600WP TPS 9.2 Environmental Limits Specification Processor Thermal Design Power (TDP) Support To allow optimal operation and long-term reliability of Intel® processor-based systems, the processor must remain within the defined minimum and maximum case temperature (TCASE) specifications. Thermal solutions not designed to provide sufficient thermal capability may affect the long-term reliability of the processor and system.
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Power Supply Specification Guidelines Intel® Server Board S2600WP TPS 10. Power Supply Specification Guidelines This section provides power supply specification guidelines recommended for providing the specified server platform with stable operating power requirements. Note: The power supply data provided in this section is for reference purposes only. It reflects Intel®’s own DC power out requirements for a 1200W and 1600W power supply as used in an Intel® designed 2U server platform.
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Intel® Server Board S2600WP TPS Power Supply Specification Guidelines Table 93. Voltage Regulation Limits Parameter +12V +5V stby 10.2.4 Tolerance - 5%/+5% - 5%/+5% Min +11.40 +4.75 Nom +12.00 +5.00 Max +12.60 +5.25 Units Vrms Vrms Dynamic Loading The output voltages shall remain within limits specified for the step loading and capacitive loading specified in the table below. The load transient repetition rate shall be tested between 50Hz and 5kHz at duty cycles ranging from 10%-90%.
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Power Supply Specification Guidelines Intel® Server Board S2600WP TPS additional heat generated, nor stressing of any internal components with this voltage applied to any individual or all outputs simultaneously. It also should not trip the protection circuits during turn on. The residual voltage at the power supply outputs for no load condition shall not exceed 100mV when AC voltage is applied and the PSON# signal is de-asserted. 10.2.
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Intel® Server Board S2600WP TPS Power Supply Specification Guidelines from 1.0 to 25ms. All outputs must rise monotonically. The following table shows the timing requirements for the power supply being turned on and off through the AC input, with PSON held low and the PSON signal, with the AC input applied. Table 97. Timing Requirements Item Tvout_rise Tsb_on_delay Description Output voltage rise time Delay from AC being applied to 5VSB being within regulation.
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Appendix A: Integration and Usage Tips Intel® Server Board S2600WP TPS Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.  This server board supports The Intel® Xeon® Processor E5-2600 and E5-2600 v2 product family with a Thermal Design Power (TDP) of up to and including 135 Watts.
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Intel® Server Board S2600WP TPS Appendix B: Integrated BMC Sensor Tables Appendix B: Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event/reading-type table information.
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Appendix B: Integrated BMC Sensor Tables  Intel® Server Board S2600WP TPS Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor.
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Intel® Server Board S2600WP TPS Appendix B: Integrated BMC Sensor Tables ® ® ® Table 98. BMC Core Sensors for Intel Server Platforms Based on Intel Xeon Processor E5 4600/2600/2400/1600 Product Families Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers 00 – Power down 02 – 240 VA power down Power Unit Status (Pwr Unit Status) 01h All Power Unit 09h Sensor Specific 6Fh 04 – A/C lost Contrib.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel® Server Board S2600WP TPS Sensor Type Event/Reading Type Event Offset Triggers Contrib. To System Status Assert/Deassert Readable Value/Offsets Event Data 07 – Redundant: Transition from nonredundant state.
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Intel® Server Board S2600WP TPS Full Sensor Name (Sensor name in SDR) BMC Watchdog Voltage Regulator Watchdog (VR Watchdog) Fan 1 Redundancy (Fan Redundancy) Sensor # 0Ah 0Bh 0Ch Platform Applicability Appendix B: Integrated BMC Sensor Tables Sensor Type Event/Reading Type All Mgmt System Health 28h Digital Discrete 03h All Voltage 02h Digital Discrete 03h Chassisspecific Fan 04h Generic 0Bh Event Offset Triggers Contrib.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Intel® Server Board S2600WP TPS Sensor # Platform Applicability Sensor Type IO Module Presence (IO Mod Presence) 0Eh Platformspecific Module/Board 15h SAS Module Presence (SAS Mod Presence) 0Fh Platformspecific BMC Firmware Health (BMC FW Health) 10h System Airflow (System Airflow) FW Update Status Event/Reading Type Event Offset Triggers Contrib.
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Intel® Server Board S2600WP TPS Full Sensor Name (Sensor name in SDR) IO Module2 Temperature (I/O Mod2 Temp) PCI Riser 3 Temperature (PCI Riser 5 Temp) PCI Riser 4 Temperature (PCI Riser 4 Temp) Baseboard +1.05V Processor3 Vccp (BB +1.05Vccp P3) Baseboard +1.05V Processor4 Vccp (BB +1.05Vccp P4) Baseboard Temperature 1 (Platform Specific) Front Panel Temperature (Front Panel Temp) SSB Temperature (SSB Temp) Revision 1.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard Temperature 2 (Platform Specific) Baseboard Temperature 3 (Platform Specific) Baseboard Temperature 4 (Platform Specific) IO Module Temperature (I/O Mod Temp) PCI Riser 1 Temperature (PCI Riser 1 Temp) IO Riser Temperature (IO Riser Temp) Hot-swap Backplane 1 Temperature (HSBP 1 Temp) Hot-swap Backplane 2 Temperature (HSBP 2 Temp) 182 Intel® Server Board S2600WP TPS Sensor # Platform Applicability Sensor Type Even
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Intel® Server Board S2600WP TPS Full Sensor Name (Sensor name in SDR) Hot-swap Backplane 3 Temperature (HSBP 3 Temp) PCI Riser 2 Temperature (PCI Riser 2 Temp) SAS Module Temperature (SAS Mod Temp) Exit Air Temperature (Exit Air Temp) Appendix B: Integrated BMC Sensor Tables Sensor # Platform Applicability Sensor Type Event/Reading Type 2Bh Chassisspecific Temperature 01h Threshold 01h 2Ch Platformspecific Temperature 01h Threshold 01h 2Dh Platformspecific Temperature 01h Threshold 01h 2Eh
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Power Supply 2 Status (PS2 Status) Power Supply 1 AC Power Input (PS1 Power In) Power Supply 2 AC Power Input (PS2 Power In) Power Supply 1 +12V % of Maximum Current Output (PS1 Curr Out %) Power Supply 2 +12V % of Maximum Current Output (PS2 Curr Out %) Power Supply 1 Temperature (PS1 Temperature) 184 Sensor # 51h Platform Applicability Chassisspecific Intel® Server Board S2600WP TPS Sensor Type Power Supply 08h Event/
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Intel® Server Board S2600WP TPS Full Sensor Name (Sensor name in SDR) Power Supply 2 Temperature (PS2 Temperature) Sensor # Platform Applicability 5Dh Chassisspecific Appendix B: Integrated BMC Sensor Tables Sensor Type Temperature Event/Reading Type Threshold 01h Event Offset Triggers [u] [c,nc] nc = Degraded c = Nonfatal 00 – Drive Presence OK 01 – Drive Fault 60h – 68h Chassisspecific 69h 6Bh Chassisspecific Microcontroller 16h Discrete 0Ah Processor 1 Status (P1 Status) 70h All P
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel® Server Board S2600WP TPS Sensor Type Event/Reading Type Threshold 01h Processor 2 Thermal Margin (P2 Therm Margin) 75h All Temperature 01h Processor 3 Thermal Margin (P3 Therm Margin) 76h Platformspecific Temperature 01h Threshold 01h 77h Platformspecific Temperature 01h Threshold 01h Processor 4 Thermal Margin (P4 Therm Margin) Processor 1 Thermal Control % (P1 Therm Ctrl
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Intel® Server Board S2600WP TPS Full Sensor Name (Sensor name in SDR) Appendix B: Integrated BMC Sensor Tables Sensor # Platform Applicability Processor 2 ERR2 Timeout (P2 ERR2) 7Dh All Processor 07h Digital Discrete 03h 01 – State Asserted Processor 3 ERR2 Timeout (P3 ERR2) 7Eh Platformspecific Processor 07h Digital Discrete 03h Processor 4 ERR2 Timeout (P4 ERR2) 7Fh Platformspecific Processor 07h Catastrophic Error (CATERR) 80h All Processor1 MSID Mismatch (P1 MSID Mismatch) 81h Pr
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel® Server Board S2600WP TPS Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Intel® Server Board S2600WP TPS Full Sensor Name (Sensor name in SDR) Processor 2 Memory VRD Hot 0-1 (P2 Mem01 VRD Hot) Processor 2 Memory VRD Hot 2-3 (P2 Mem23 VRD Hot) Processor 3 Memory VRD Hot 0-1 (P3 Mem01 VRD Hot) Processor 3 Memory VRD Hot 2-3 (P4 Mem23 VRD Hot) Processor 4 Memory VRD Hot 0-1 (P4 Mem01 VRD Hot) Processor 4 Memory VRD Hot 2-3 (P4 Mem23 VRD Hot) Power Supply 1 Fan Tachometer 1 (PS1 Fan Tach 1) Power Supply 1 Fan Tachometer 2 (PS1 Fan Tach 2) Revision 1.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Power Supply 2 Fan Tachometer 1 (PS2 Fan Tach 1) Power Supply 2 Fan Tachometer 2 (PS2 Fan Tach 2) Processor 1 DIMM Aggregate Thermal Margin 1 (P1 DIMM Thrm Mrgn1) Processor 1 DIMM Aggregate Thermal Margin 2 (P1 DIMM Thrm Mrgn2) Processor 2 DIMM Aggregate Thermal Margin 1 (P2 DIMM Thrm Mrgn1) Processor 2 DIMM Aggregate Thermal Margin 2 (P2 DIMM Thrm Mrgn2) Processor 3 DIMM Aggregate Thermal Margin 1 (P3 DIMM Thrm Mrgn1) 190 Inte
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Intel® Server Board S2600WP TPS Full Sensor Name (Sensor name in SDR) Processor 3 DIMM Aggregate Thermal Margin 2 (P3 DIMM Thrm Mrgn2) Processor 4 DIMM Aggregate Thermal Margin 1 (P4 DIMM Thrm Mrgn1) Processor 4 DIMM Aggregate Thermal Margin 2 (P4 DIMM Thrm Mrgn2) Fan Tachometer Sensors (Chassis specific sensor names) Processor 1 DIMM Thermal Trip (P1 Mem Thrm Trip) Processor 2 DIMM Thermal Trip (P2 Mem Thrm Trip) Processor 3 DIMM Thermal Trip (P3 Mem Thrm Trip) Revision 1.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 4 DIMM Thermal Trip (P4 Mem Thrm Trip) Global Aggregate Temperature Margin 1 (Agg Therm Mrgn 1) Global Aggregate Temperature Margin 2 (Agg Therm Mrgn 2) Global Aggregate Temperature Margin 3 (Agg Therm Mrgn 3) Global Aggregate Temperature Margin 4 (Agg Therm Mrgn 4) Global Aggregate Temperature Margin 5 (Agg Therm Mrgn 5) 192 Sensor # Platform Applicability C3h All C8h Platform Specific Intel® Server Board S2600
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Intel® Server Board S2600WP TPS Full Sensor Name (Sensor name in SDR) Global Aggregate Temperature Margin 6 (Agg Therm Mrgn 6) Global Aggregate Temperature Margin 7 (Agg Therm Mrgn 7) Global Aggregate Temperature Margin 8 (Agg Therm Mrgn 8) Baseboard +12V (BB +12.0V) Baseboard +5V (BB +5.0V) Baseboard +3.3V (BB +3.3V) Baseboard +5V Stand-by (BB +5.0V STBY) Revision 1.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard +3.3V Auxiliary (BB +3.3V AUX) Baseboard +1.05V Processor1 Vccp (BB +1.05Vccp P1) Baseboard +1.05V Processor2 Vccp (BB +1.05Vccp P2) Baseboard +1.5V P1 Memory AB VDDQ (BB +1.5 P1MEM AB) Baseboard +1.5V P1 Memory CD VDDQ (BB +1.5 P1MEM CD) Baseboard +1.5V P2 Memory AB VDDQ (BB +1.
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Intel® Server Board S2600WP TPS Full Sensor Name (Sensor name in SDR) Baseboard +1.5V P2 Memory CD VDDQ (BB +1.5 P2MEM CD) Baseboard +1.8V Aux (BB +1.8V AUX) Baseboard +1.1V Stand-by (BB +1.1V STBY) Baseboard CMOS Battery (BB +3.3V Vbat) Baseboard +1.35V P1 Low Voltage Memory AB VDDQ (BB +1.35 P1LV AB) Baseboard +1.35V P1 Low Voltage Memory CD VDDQ (BB +1.35 P1LV CD) Baseboard +1.35V P2 Low Voltage Memory AB VDDQ (BB +1.35 P2LV AB) Revision 1.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard +1.35V P2 Low Voltage Memory CD VDDQ (BB +1.35 P2LV CD) Baseboard +3.3V Riser 1 Power Good (BB +3.3 RSR1 PGD) Baseboard +3.3V Riser 2 Power Good (BB +3.
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Intel® Server Board S2600WP TPS Appendix B: Integrated BMC Sensor Tables IPMI Channel ID Assignments Below table provides the information of BMC channels’ assignments: Table 99.
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Appendix B: Integrated BMC Sensor Tables Intel® Server Board S2600WP TPS Temperature: ® Table 101.
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Intel® Server Board S2600WP TPS Appendix B: Integrated BMC Sensor Tables Chassis-specific sensors ® Table 102.
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Appendix B: Integrated BMC Sensor Tables Intel® Server Chassis Fan Domain Intel® Server Board S2600WP TPS Major Components Cooled (Temperature sensor number) PS1 Temperature (5C) Fans (Sensor number) PS1 1b Fan Fail (A1h) PS2 Temperature (5D) PS2 1a Fan Fail (A4h) PS2 1b Fan Fail (A5h) HSC Availability  FH2K16X25HSBP(PBA# G16566-XXX) for 16x2.5" HDD used in H2216WPJR/KR  FH2K12X35HSBP(PBA# G16567-XXX) for 12x3.5" HDD used in H2312WPJR/KR Power unit and Power Supply support ® Table 104.
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Intel® Server Board S2600WP TPS Appendix C: BIOS Sensors and SEL Data Appendix C: BIOS Sensors and SEL Data BIOS owns a set of IPMI-compliant Sensors. These are actually divided in ownership between BIOS POST (GID = 01) and BIOS SMI Handler (GID = 33). The SMI Handler Sensors are typically for logging runtime error events, but they are active during POST and may log errors such as Correctable Memory ECC Errors if they occur.
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Appendix C: BIOS Sensors and SEL Data Sensor Name Memory RAS Configuration Status Sensor Number 02h Intel® Server Board S2600WP TPS Sensor Owner (GID) 01h (BIOS POST) Sensor Type 0Ch (Memory) Event/Reading Type Offset Values 09h (Digital Discrete) 0h = RAS Configuration Disabled 1h = RAS Configuration Enabled Event Data 2 Event Data 3 ED2 = [7:4] = Reserved [3:0] Config Err 0 = None 3 = Invalid DIMM Config for RAS Mode ED3 = [7:4] = Reserved [3:0] = RAS Mode 0 = None 1 = Mirroring 2 = Lockstep 4 = Ran
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Intel® Server Board S2600WP TPS Sensor Name PCIe Fatal Error (Standard AER Errors) (see Sensor 14h for continuation) Sensor Number 04h Appendix C: BIOS Sensors and SEL Data Sensor Owner (GID) 33h (SMI Handler) Sensor Type 13h (Critical Interrupt) Event/Reading Type Offset Values 70h (OEM Discrete) 0h = Data Link Layer Protocol Error 1h = Surprise Link Down Error 2h = Completer Abort 3h = Unsupported Request 4h = Poisoned TLP 5h = Flow Control Protocol 6h = Completion Timeout 7h = Receiver Buffer Overflo
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Appendix C: BIOS Sensors and SEL Data Sensor Name Sensor Number Intel® Server Board S2600WP TPS Sensor Owner (GID) Sensor Type for continuation) Event/Reading Type Offset Values Uncorrectable ECC Error 1h = Protocol Layer Poisoned Packet Reception Error 2h = Link/PHY Init Failure with resultant degradation in link width 3h = CSI PHY Layer detected drift buffer alarm 4h = CSI PHY detected latency buffer rollover 5h = CSI PHY Init Failure 6h = CSI Link Layer generic control error (buffer overflow/underf
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Intel® Server Board S2600WP TPS Sensor Name Sparing Redundancy State Memory RAS Mode Select Revision 1.
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Appendix C: BIOS Sensors and SEL Data Sensor Name Memory Parity Error PCIe Fatal Error#2 (Standard AER Errors) (continuation of Sensor 04h) 206 Sensor Number 13h 14h Intel® Server Board S2600WP TPS Sensor Owner (GID) 33h (SMI Handler) 33h (SMI Handler) Sensor Type 0Ch (Memory) 13h (Critical Interrupt) Event/Reading Type Offset Values 6Fh (Sensor Specific Offset) 2h = Address Parity Error Event Data 2 Event Data 3 ED2 = Validity [7:5] = Reserved [4] = Channel Validity Check 0 = ED3 Chan # Not Vali
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Intel® Server Board S2600WP TPS Sensor Name QPI Fatal Error (continuation of Sensor 07h) Sensor Number 17h Appendix C: BIOS Sensors and SEL Data Sensor Owner (GID) 33h (SMI Handler) Sensor Type 13h (Critical Interrupt) Event/Reading Type Offset Values 74h (OEM Discrete) 0h = Illegal inbound request 1h = IIO Write Cache Uncorrectable Data ECC Error 2h = IIO CSR crossing 32-bit boundary Error 3h = IIO Received XPF physical/logical redirect interrupt inbound 4h = IIO Illegal SAD or Illegal or non-existent
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Appendix D: POST Code LED Decoder Intel® Server Board S2600WP TPS Appendix D: POST Code LED Decoder During the system boot process, the BIOS executes several platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code on the POST code diagnostic LEDs found on the back edge of the server board.
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Intel® Server Board S2600WP TPS Appendix D: POST Code LED Decoder In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows: Table 106.
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Appendix D: POST Code LED Decoder Intel® Server Board S2600WP TPS Table 108.
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Intel® Server Board S2600WP TPS Appendix D: POST Code LED Decoder Progress Code Description 0x08 Early NB initialization during Sec Phase 0x09 End Of Sec Phase 0x0E Microcode Not Found 0x0F Microcode Not Loaded PEI Phase 0x10 PEI Core 0x11 CPU PEIM 0x15 NB PEIM 0x19 SB PEIM MRC Progress Codes At this point the MRC Progress Code sequence is executed See Table 106 0x31 Memory Installed 0x32 CPU PEIM (CPU Init) 0x33 CPU PEIM (Cache Init) 0x34 CPU PEIM (BSP Select) 0x35 CPU PEIM (AP
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Appendix D: POST Code LED Decoder Intel® Server Board S2600WP TPS Progress Code 212 Description 0x79 DXE CSM Init 0x90 DXE BDS Started 0x91 DXE BDS connect drivers 0x92 DXE PCI Bus begin 0x93 DXE PCI Bus HPC Init 0x94 DXE PCI Bus enumeration 0x95 DXE PCI Bus resource requested 0x96 DXE PCI Bus assign resource 0x97 DXE CON_OUT connect 0x98 DXE CON_IN connect 0x99 DXE SIO Init 0x9A DXE USB start 0x9B DXE USB reset 0x9C DXE USB detect 0x9D DXE USB enable 0xA1 DXE IDE begin
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Intel® Server Board S2600WP TPS Appendix D: POST Code LED Decoder Progress Code Description 0xB2 DXE Legacy Option ROM init 0xB3 DXE Reset system 0xB4 DXE USB Hot plug 0xB5 DXE PCI BUS Hot plug 0xB6 DXE NVRAM cleanup 0xB7 DXE Configuration Reset 0x00 INT19 S3 Resume 0xE0 S3 Resume PEIM (S3 started) 0xE1 S3 Resume PEIM (S3 boot script) 0xE2 S3 Resume PEIM (S3 Video Repost) 0xE3 S3 Resume PEIM (S3 OS wake) BIOS Recovery Revision 1.
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Appendix E: Video POST Code Errors Intel® Server Board S2600WP TPS Appendix E: Video POST Code Errors Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware being initialized. The operation field represents the specific initialization activity.
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Intel® Server Board S2600WP TPS Appendix E: Video POST Code Errors Error Code 8161 Error Message Processor 02 unable to apply microcode update Response Major 8162 Processor 03 unable to apply microcode update Major 8163 Processor 04 unable to apply microcode update Major 8170 Processor 01 failed Self Test (BIST) Major 8171 Processor 02 failed Self Test (BIST) Major 8172 Processor 03 failed Self Test (BIST) Major 8173 Processor 04 failed Self Test (BIST) Major 8180 Processor 01 microc
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Appendix E: Video POST Code Errors Intel® Server Board S2600WP TPS Error Code 8536 DIMM_H2 failed test/initialization Response Major 8537 DIMM_H3 failed test/initialization Major 8538 DIMM_J1 failed test/initialization Major 8539 DIMM_J2 failed test/initialization Major 853A DIMM_J3 failed test/initialization Major 853B DIMM_K1 failed test/initialization Major 853C DIMM_K2 failed test/initialization Major 853D DIMM_K3 failed test/initialization Major 853E DIMM_L1 failed test/initi
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Intel® Server Board S2600WP TPS Appendix E: Video POST Code Errors Error Code 8560 Error Message DIMM_A1 encountered a Serial Presence Detection (SPD) failure Response Major 8561 DIMM_A2 encountered a Serial Presence Detection (SPD) failure Major 8562 DIMM_A3 encountered a Serial Presence Detection (SPD) failure Major 8563 DIMM_B1 encountered a Serial Presence Detection (SPD) failure Major 8564 DIMM_B2 encountered a Serial Presence Detection (SPD) failure Major 8565 DIMM_B3 encountered a S
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Appendix E: Video POST Code Errors Intel® Server Board S2600WP TPS Error Code 85CB DIMM_R2 failed test/initialization Response Major 85CC DIMM_R3 failed test/initialization Major 85CD DIMM_T1 failed test/initialization Major 85CE DIMM_T2 failed test/initialization Major 85CF DIMM_T3 failed test/initialization Major 85D0 DIMM_L3 disabled Major 85D1 DIMM_M1 disabled Major 85D2 DIMM_M2 disabled Major 85D3 DIMM_M3 disabled Major 85D4 DIMM_N1 disabled Major 85D5 DIMM_N2 disabled
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Intel® Server Board S2600WP TPS Appendix E: Video POST Code Errors Error Code A002 TPM device failure. Response Minor A003 TPM device failed self test. Minor A100 BIOS ACM Error Major A421 PCI component encountered a SERR error Fatal A5A0 PCI Express component encountered a PERR error Minor A5A1 PCI Express component encountered an SERR error Fatal A6A0 DXE Boot Services driver: Not enough memory available to shadow a Legacy Option ROM. Minor Revision 1.
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Glossary Intel® Server Board S2600WP TPS Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) with alpha entries following (for example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following. Table 111.
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Intel® Server Board S2600WP TPS Glossary Term HPA Host Physical Address Hz Hertz (1 cycle/second) 2 Definition IC Inter-Integrated Circuit Bus IA Intel Architecture IBF Input Buffer IBIST Interconnect Built-in Self-Test ICH I/O Controller Hub IC MB Intelligent Chassis Management Bus IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platfo
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Glossary 222 Intel® Server Board S2600WP TPS Term PSMI Power Supply Management Interface Definition PWM Pulse-Width Modulation QPI QuickPath Interconnect RAM Random Access Memory RASUM Reliability, Availability, Serviceability, Usability, and Manageability RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real-Time Clock (Component of ICH peripheral chip on the server board) RMM3 Remote Management Module 3 SDR Sensor Data Record SECC Single Edge Connector Cartridge SE
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Intel® Server Board S2600WP TPS Reference Documents Reference Documents  ACPI 3.0: http://www.acpi.info/spec.htm  IPMI 2.0  Data Center Management Interface Specification v1.0, May 1, 2008: www.intel.com/go/dcmi  PCI Bus Power Management Interface Specification, 1.1: http://www.pcisig.com/  PCI Express* Base Specification, Rev 2.0, Dec 06: http://www.pcisig.com/  PCI Express* Card Electromechanical Specification, Rev 2.0: http://www.pcisig.com/  PMBus*: http://pmbus.org  SATA 2.