Technical Product Specification

Intel
®
Server System H2000WP Family TPS Power Sub-System
3.3.14 Forced Load Sharing
The +12V output will have active load sharing. The output will share within 10% at full load. The
failure of a power supply should not affect the load sharing or output voltages of the other
supplies still operating. The supplies must be able to load share in parallel and operate in a hot-
swap/redundant 1+1 configurations. The 12VSBoutput is not required to actively share current
between power supplies (passive sharing). The 12VSBoutput of the power supplies are
connected together in the system so that a failure or hot swap of a redundant power supply
does not cause these outputs to go out of regulation in the system.
3.3.15 Timing Requirement
These are the timing requirements for the power supply operation. The output voltages must
rise from 10% to within regulation limits (T
vout_rise
) within 5 to 70ms. For 12VSB, it is allowed to
rise from 1.0 to 25ms. All outputs must rise monotonically. The following table shows the
timing requirements for the power supply being turned on and off through the AC input, with
PSON held low and the PSON signal, with the AC input applied.
Table 26. Timing Requirement
Item
Description
MIN
MAX
UNITS
T
vout_rise
Output voltage rise time
5.0 *
70 *
ms
T
sb_on_delay
Delay from AC being applied to 12VSB being within regulation.
1500
ms
T
ac_on_delay
Delay from AC being applied to all output voltages being within
regulation
3000
ms
T
vout_holdup
Time 12Vl output voltage stay within regulation after loss of AC
13
ms
T
pwok_holdup
Delay from loss of AC to de-assertion of PWOK
10.6
ms
T
pson_on_delay
Delay from PSON# active to output voltages within regulation
limits
5
400
ms
T
pson_pwok
Delay from PSON# deactivate to PWOK being de-asserted
5
ms
T
pwok_on
Delay from output voltages within regulation limits to PWOK
asserted at turn on
100
500
ms
T
pwok_off
Delay from PWOK de-asserted to output voltages dropping out
of regulation limits
1
ms
T
pwok_low
Duration of PWOK being in the de-asserted state during an
off/on cycle using AC or the PSON signal
100
ms
T
sb_vout
Delay from 12VSBbeing in regulation to O/Ps being in
regulation at AC turn on
50
1000
ms
T
12VSB_holdup
Time the 12VSBoutput voltage stays within regulation after loss
of AC
70
ms
Note: * The 12V
STB
output voltage rise time should be from 1.0ms to 25ms.
Revision 1.6 Intel order number: G52418-006 29