Technical Product Specification

Intel® Server Board S2600CO Family TPS Functional Architecture Overview
Revision 1.6 21
Intel order number G42278-004
The physical connectivity of each interconnect link is made up of twenty differential signal pairs
plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional
links to complete the connection between two components. This supports traffic in both
directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as
having five layers: Physical, Link, Routing, Transport, and Protocol.
The Intel
®
QuickPath Interconnect includes a cache coherency protocol to keep the distributed
memory and caching structures coherent during system operation. It supports both low-latency
source snooping and a scalable home snoop behavior. The coherency protocol provides for
direct cache-to-cache transfers for optimal latency.
3.2.2 Integrated Memory Controller (IMC) and Memory Subsystem
Intel® Xeon®
E5-2600
CPU 1
DDR3 MEMORY
2 DIMMs/channel
CHANNEL 0
Intel® Xeon®
E5-2600
CPU2
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
DDR3 MEMORY
2 DIMMs/channel
QPI
QPI
P2 P1P3P0
IOU0 IOU2IOU1
P1
P3
P2P0
IOU2
IOU1
IOU0
Figure 12. Integrated Memory Controller Functional Block Diagram
Integrated into the processor is a memory controller. Each processor provides four DDR3
channels that support the following:
 Unbuffered DDR3 and registered DDR3 DIMMs
 LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher
capacity memory subsystems
 Independent channel mode or lockstep mode
 Data burst length of eight cycles for all memory organization modes
 Memory DDR3 data transfer rates of 800, 1066, 1333, 1600 and 1866 MT/s
Note: 1866MT/s is only supported for Intel® Xeon® processor E5-2600 v2 product family
 64-bit wide channels plus 8-bits of ECC support for each channel
 DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V
 1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices:
o UDIMM DDR3 – SR x8 and x16 data widths, DR – x8 data width
o RDIMM DDR3 – SR, DR, and QR – x4 and x8 data widths
o LRDIMM DDR3 – QR – x4 and x8 data widths with direct map or with rank
multiplication
 Up to 8 ranks supported per memory channel, 1, 2, or 4 ranks per DIMM
 Open with adaptive idle page close timer or closed page policy
 Per channel memory test and initialization engine can initialize DRAM to all logical zeros
with valid ECC (with or without data scrambler) or a predefined test pattern
 Isochronous access support for Quality of Service (QoS)