Technical Product Specification

Product Architecture Overview Intel
®
Server Board S2400EP TPS
Intel order number G50763-002 Revision 2.0
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However, before returning control to the OS drivers via Machine Check Exception (MCE) or
Non-Maskable Interrupt (NMI), the Uncorrectable Memory ECC Error is logged to the SEL, the
appropriate memory slot fault LED is lit, and the System Status LED state is changed to
solid Amber.
3.2.2.8 Demand Scrubbing for ECC Memory
Demand scrubbing is the ability to write corrected data back to the memory once a correctable
error is detected on a read transaction. This allows for correction of data in memory at detect,
and decrease the chances of a second error on the same address accumulating to cause a
multi-bit error (MBE) condition.
Demand Scrubbing is enabled/disabled (default is enabled) in the Memory Configuration screen
in Setup.
3.2.2.9 Patrol Scrubbing for ECC Memory
Patrol scrubs are intended to ensure that data with a correctable error does not remain in
DRAM long enough to stand a significant chance of further corruption to an
uncorrectable stage.
3.2.3 Processor Integrated I/O Module (IIO)
The processor’s integrated I/O module provides features traditionally supported through chipset
components. The integrated I/O module provides the following features:
 PCI Express* Interfaces: The integrated I/O module incorporates the PCI Express*
interface and supports up to 24 lanes of PCI Express*. Following are key attributes of
the PCI Express* interface:
o Gen3 speeds at 8 GT/s (no 8b/10b encoding)
o X16 interface
o X8 interface
 DMI2 Interface to the PCH: The platform requires an interface to the legacy
Southbridge (PCH) which provides basic, legacy functions required for the server
platform and operating systems. Since only one PCH is required and allowed for the
system, any sockets which do not connect to PCH would use this port as a standard x4
PCI Express* 2.0 interface.
 Integrated IOAPIC: Provides support for PCI Express* devices implementing legacy
interrupt messages without interrupt sharing.
 Non Transparent Bridge: PCI Express* non-transparent bridge (NTB) acts as a
gateway that enables high performance, low overhead communication between two
intelligent subsystems; the local and the remote subsystems. The NTB allows a local
processor to independently configure and control the local subsystem, provides isolation
of the local host memory domain from the remote host memory domain while enabling
status and data exchange between the two domains.
 Intel
®
QuickData Technology: Used for efficient, high bandwidth data movement
between two locations in memory or from memory to I/O.