Technical Product Specification

Product Architecture Overview Intel
®
Server Board S2400EP TPS
Intel order number G50763-002 Revision 2.0
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3.2.2.4.3 Mirrored Channel Mode
Channel Mirroring Mode gives the best memory RAS capability by maintaining two copies of the
data in main memory. If there is an Uncorrectable ECC Error, the channel with the error is
disabled and the system continues with the “good” channel, but in a non-redundant
configuration.
For Mirroring mode to be to be available as a RAS option, the DIMM population must be
identical between each pair of memory channels that participate. Not all channel pairs need to
have memory installed, but for each pair, the configuration must match. If the configuration is
not matched up properly, the memory operating mode falls back to Independent Channel Mode.
Mirroring Mode is enabled/disabled in the Memory RAS and Performance Configuration screen
in the <F2> BIOS Setup Utility.
When Mirroring Mode is operational, each channel in a pair is “mirrored” by the other channel.
The impact on Effective Memory size is to reduce by half the total amount of installed memory
available for use.
When Mirroring Mode is operational, the system treats Correctable Errors the same way as it
would in Independent channel mode. There is a correctable error threshold. Correctable error
counts accumulate by rank, and the first event is logged.
What Mirroring primarily protects against is the possibility of an Uncorrectable ECC Error
occurring with critical data “in process”. Without Mirroring, the system would be expected to
“Blue Screen” and halt, possibly with serious impact to operations. But with Mirroring Mode in
operation, an Uncorrectable ECC Error from one channel becomes a Mirroring Fail Over (MFO)
event instead, in which the IMC retrieves the correct data from the “mirror image” channel and
disables the failed channel. Since the ECC Error was corrected in the process of the MFO
Event, the ECC Error is demoted to a Correctable ECC Error. The channel pair becomes a
single non-redundant channel, but without impacting operations, and the Mirroring Fail Over
Event is logged to SEL to alert the user that there is memory hardware that has failed and
needs to be replaced.
3.2.2.5 Lockstep Channel Mode
In lockstep channel mode the cache-line is split across channels. This is done to support Single
Device Data Correction (SDDC) for DRAM devices with 8-bit wide data ports. Also, the same
address is used on both channels, such that an address error on any channel is detectable by
bad ECC. The iMC module always accumulates 32-bytes before forwarding data so there is no
latency benefit for disabling ECC.
Lockstep channels must be populated identically. That is, each DIMM in one channel must have
a corresponding DIMM of identical organization (number ranks, number banks, number rows,
number columns). DIMMs may be of different speed grades, but the iMC module will be
configured to operate all DIMMs according to the slowest parameters present by the Memory
Reference Code (MRC).
Performance in lockstep mode cannot be as high as with independent channels. The burst
length for DDR3 DIMMs is eight which is shared between two channels that are in lockstep
mode. Each channel of the pair provides 32 bytes to produce the 64-byte cache-line. DRAMs