Technical Product Specification

Intel

Server Board S2400EP TPS Product Architecture Overview

Revision 2.0 Intel order number G50763-002

population between channels (Mirrored and Lockstep) require that ECC DIMMs be populated.

Independent Channel Mode is the only mode that supports non-ECC DIMMs in addition to

ECC DIMMs.

For RAS modes that require matching populations, the same slot positions across channels

must hold the same DIMM type with regards to size and organization. DIMM timings do not

have to match but timings will be set to support all DIMMs populated (that is, DIMMs with slower

timings will force faster DIMMs to the slower common timing modes).

3.2.2.4.1 Independent Channel Mode

In non-ECC and x4 SDDC configurations, each channel is running independently (nonlock-step),

that is, each cache-line from memory is provided by a channel. To deliver the 64-byte cache-

line of data, each channel is bursting eight 8-byte chunks. Back to back data transfer in the

same direction and within the same rank can be sent back-to-back without any dead-cycle. The

independent channel mode is the recommended method to deliver most efficient power and

bandwidth as long as the x8 SDDC is not required.

3.2.2.4.2 Rank Sparing Mode

Rank Sparing Mode enhances the system’s RAS capability by “swapping out” failing ranks of

DIMMs. Rank Sparing is strictly channel and rank oriented. Each memory channel is a

Sparing Domain.

For Rank Sparing to be available as a RAS option, there must be 2 or more single rank or dual

rank DIMMs, or at least one quad rank DIMM installed on each memory channel.

Rank Sparing Mode is enabled/disabled in the Memory RAS and Performance Configuration

screen in the <F2> Bios Setup Utility.

When Sparing Mode is operational, for each channel, the largest size memory rank is reserved

as a “spare” and is not used during normal operations. The impact on Effective Memory Size is

to subtract the sum of the reserved ranks from the total amount of installed memory.

Hardware registers count the number of Correctable ECC Errors for each rank of memory on

each channel during operations and compare the count against a Correctable Error Threshold.

When the correctable error count for a given rank hits the threshold value, that rank is deemed

to be “failing”, and it triggers a Sparing Fail Over (SFO) event for the channel in which that rank

resides. The data in the failing rank is copied to the Spare Rank for that channel, and the Spare

Rank replaces the failing rank in the IMC’s address translation registers.

An SFO Event is logged to the BMC SEL. The failing rank is then disabled, and any further

Correctable Errors on that now non-redundant channel will be disregarded.

The correctable error that triggered the SFO may be logged to the BMC SEL, if it was the first

one to occur in the system. That first correctable error event will be the only one logged for the

system. However, since each channel is a Sparing Domain, the correctable error counting

continues for other channels which are still in a redundant state. There can be as many SFO

Events as there are memory channels with DIMMs installed.