Technical Product Specification

Product Architecture Overview Intel
®
Server Board S2400EP TPS
Intel order number G50763-002 Revision 2.0
24
o LRDIMM DDR3 QR x4 and x8 data widths with direct map or with rank
multiplication
Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM
Open with adaptive idle page close timer or closed page policy
Per channel memory test and initialization engine can initialize DRAM to all logical zeros
with valid ECC (with or without data scrambler) or a predefined test pattern
Isochronous access support for Quality of Service (QoS)
Minimum memory configuration: independent channel support with 1 DIMM populated
Integrated dual SMBus* master controllers
Command launch modes of 1n/2n
RAS Support:
o Rank Level Sparing and Device Tagging
o Demand and Patrol Scrubbing
o DRAM Single Device Data Correction (SDDC) for any single x4 or x8
DRAM device. Independent channel mode supports x4 SDDC. x8 SDDC
requires lockstep mode
o Lockstep mode where channels 0 and 1 and channels 2 and 3 are
operated in lockstep mode
o Data scrambling with address to ease detection of write errors to an
incorrect address.
o Error reporting via Machine Check Architecture
o Read Retry during CRC error handling checks by iMC
o Channel mirroring within a socket
- CPU1 Channel Mirror Pairs B and C
- CPU2 Channel Mirror Pairs E and F
o Error Containment Recovery
Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
Memory thermal monitoring support for DIMM temperature
3.2.2.1 Supported Memory
Table 3. UDIMM Support Guidelines (Preliminary. Subject to Change)
Ranks
Per
DIMM
and
Data
Width
Memory Capacity Per
DIMM1
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)
2,3
1 Slot per Channel
2 Slots per Channel
1DPC
1DPC
2DPC
1.35V
1.5V
1.35V
1.5V
1.35V
1.5V
SRx8
Non-
ECC
1GB
2GB
4GB
n/a
1066, 1333
n/a
1066, 1333
n/a
1066
DRx8
Non-
ECC
2GB
4GB
8GB
n/a
1066, 1333
n/a
1066, 1333
n/a
1066
SRx16
Non-
ECC
512MB
1GB
2GB
n/a
1066, 1333
n/a
1066, 1333
n/a
1066