Technical Product Specification

Product Architecture Overview Intel
®
Server Board S2400EP TPS
Intel order number G50763-002 Revision 2.0
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 When one DIMM is used, it must be populated in the BLUE DIMM slot (farthest away
from the CPU) of a given channel.
 When single, dual and quad rank DIMMs are populated for 2DPC, always populate the
higher number rank DIMM first (starting from the farthest slot), for example, first quad
rank, then dual rank, and last single rank DIMM.
3.2.2.3 Publishing System Memory
 The BIOS displays the “Total Memory” of the system during POST if Display Logo is
disabled in the BIOS setup. This is the total size of memory discovered by the BIOS
during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in
the system.
 The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term
Effective Memory refers to the total size of all DDR3 DIMMs that are active (not disabled)
and not used as redundant units.
 The BIOS provides the total memory of the system in the main page of the BIOS setup.
This total is the same as the amount described by the first bullet above.
 If Display Logo is disabled, the BIOS displays the total system memory on the
diagnostic screen at the end of POST. This total is the same as the amount described
by the first bullet above.
Note: Some server operating systems do not display the total physical memory installed. What
is displayed is the amount of physical memory minus the approximate memory space used by
system BIOS components. These BIOS components include, but are not limited to:
 ACPI (may vary depending on the number of PCI devices detected in the system)
 ACPI NVS table
 Processor microcode
 Memory Mapped I/O (MMIO)
 Manageability Engine (ME)
 BIOS flash
3.2.2.4 Integrated Memory Controller Operating Modes and RAS Support
The server board supports the following memory RAS modes:
 Independent Channel Mode
 Rank Sparing Mode
 Mirrored Channel Mode
 Lockstep Channel Mode
 Single Device Data Correction (SDDC)
 Error Correction Code (ECC) Memory
 Demand Scrubbing for ECC Memory
 Patrol Scrubbing for ECC Memory
Regardless of RAS mode, the requirements for populating within a channel given in the section
3.2.2.2 must be met at all times. Note that support of RAS modes that require matching DIMM