Technical Product Specification

Intel® Server Board S1400SP TPS Functional Architecture
Revision 2.1 Intel order number G64248-003 33
 ECC Error Reporting. When detecting an ECC error, the host controller has the ability
to send one of several messages to the chipset. The host controller can instruct the
chipset to generate SMI #, NMI, SERR#, or TCO interrupt.
 Function Disable. The chipset provides the ability to disable the following integrated
functions: LAN, USB, LPC, SATA, PCI Express* or SMBus*. Once disabled, these
functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts
or power management events are generated from the disabled functions.
 Intruder Detect. The chipset provides an input signal (INTRUDER#) that can be attached
to a switch that is activated by the system case being opened. The chipset can be
programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal.
3.4 Integrated Baseboard Management Controller (BMC) Overview
The server board utilizes the I/O controller, Graphics Controller, and Baseboard Management
features of the Server Engines* Pilot-III Server Management Controller. The following is an
overview of the features as implemented on the server board from each embedded controller.
Figure 22. Integrated Baseboard Management Controller (BMC) Overview