Technical Product Specification

Functional Architecture Intel® Server Board S1400SP TPS
16 Intel order number G64248-003 Revision 2.1
The following sections will provide an overview of the key processor features and functions that
help to define the performance and architecture of the server board.
Processor Feature Details:
 Up to 8 execution cores (Intel
®
Xeon
®
processor E5-2400 product family)
 Up to 10 execution cores (Intel
®
Xeon
®
processor E5-2400 v2 product family)
 Each core supports two threads (Intel
®
Hyper-Threading Technology)
 46-bit physical addressing and 48-bit virtual addressing
 1GB large page support for server applications
 A 32KB instruction and 32KB data first-level cache (L1) for each core
 A 256KB shared instruction/data mid-level (L2) cache for each core
 Up to 20MB last level cache (LLC): up to 2.5MB per core instruction/data last level cache
(LLC), shared among all cores
Supported Technologies:
 Intel
®
Virtualization Technology (Intel
®
VT)
 Intel
®
Virtualization Technology for Directed I/O (Intel
®
VT-d)
 Intel
®
Trusted Execution Technology (Intel
®
TXT)
 Intel
®
64 Architecture
 Intel
®
Streaming SIMD Extensions 4.1 (Intel
®
SSE4.1)
 Intel
®
Streaming SIMD Extensions 4.2 (Intel
®
SSE4.2)
 Intel
®
Advanced Vector Extensions (Intel
®
AVX)
 Intel
®
Hyper-Threading Technology
 Execute Disable Bit
 Intel
®
Turbo Boost Technology
 Intel
®
Intelligent Power Technology
 Enhanced Intel
®
SpeedStep Technology
 Intel
®
Data Direct I/O (DDIO) Technology
3.2.1 Intel
®
QuickPath Interconnect
The Intel
®
QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used
in the processor. The narrow high-speed links stitch together processors in distributed shared
memory and integrated I/O platform architecture. It offers much higher bandwidth with low
latency. The Intel
®
QuickPath Interconnect has an efficient architecture allowing more
interconnect performance to be achieved in real systems. It has a snoop protocol optimized for
low latency and high scalability, as well as packet and lane structures enabling quick
completions of transactions. Reliability, availability, and serviceability features (RAS) are built into
the architecture.
The physical connectivity of each interconnect link is made up of twenty differential signal pairs
plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional