Technical Product Specification

Functional Architecture Intel® Server Board S1400FP TPS
32 Intel order number G64246-003 Revision 2.0
configurable transmit and receive FIFOs (up to 20 KB each) help prevent data underruns and
overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit
data with minimum interframe spacing (IFS).
The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either full duplex
or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow
Control Specification. Half duplex performance is enhanced by a proprietary collision reduction
mechanism.
3.3.13
RTC
The C600 chipset contains a Motorola MC146818B-compatible real-time clock with 256 bytes of
battery-backed RAM. The real-time clock performs two key functions: keeping track of the time
of day and storing system data, even when the system is powered down. The RTC operates on
a 32.768 KHz crystal and a 3 V battery. The RTC also supports two lockable memory ranges.
By setting bits in the configuration space, two 8-byte ranges can be locked to read and write
accesses. This prevents unauthorized reading of passwords or other system security
information. The RTC also supports a date alarm that allows for scheduling a wake up event up
to 30 days in advance, rather than just 24 hours in advance.
3.3.14
GPIO
Various general purpose inputs and outputs are provided for custom system design. The
number of inputs and outputs varies depending on the C600 chipset configuration.
3.3.15
Enhanced Power Management
The C600 chipset’s power management functions include enhanced clock control and various
low-power (suspend) states (for example, Suspend-to-RAM and Suspend-to-Disk). A hardware-
based thermal management circuit permits software-independent entrance to low-power states.
The C600 chipset contains full support for the Advanced Configuration and Power Interface
(ACPI).
3.3.16
Manageability
The chipset integrates several functions designed to manage the system and lower the total
cost of ownership (TCO) of the system. These system management functions are designed to
report errors, diagnose the system, and recover from system lockups without the aid of an
external microcontroller.
 TCO Timer. The chipset’s integrated programmable TCO timer is used to detect system
locks. The first expiration of the timer generates an SMI# that the system can use to
recover from a software lock. The second expiration of the timer causes a system reset
to recover from a hardware lock.
 Processor Present Indicator. The chipset looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the chipset will
reboot the system.
 ECC Error Reporting. When detecting an ECC error, the host controller has the ability
to send one of several messages to the chipset. The host controller can instruct the
chipset to generate SMI#, NMI, SERR#, or TCO interrupt.