Technical Product Specification

Intel® Server Board S1400FP TPS Functional Architecture
Revision 2.0 Intel order number G64246-003 31
3.3.8
Serial Peripheral Interface (SPI)
The C600 chipset implements an SPI Interface as an alternative interface for the BIOS flash
device. An SPI flash device can be used as a replacement for the FWH, and is required to
support Gigabit Ethernet and Intel
®
Active Management Technology. The C600 chipset supports
up to two SPI flash devices with speeds up to 50 MHz, utilizing two chip select pins.
3.3.9
Compatibility Modules (DMA Controller, Timer/Counters, and Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers. Channel 4 is
reserved as a generic bus master request.
The C600 chipset supports LPC DMA, which is similar to ISA DMA, through the C600 chipset’s
DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and
special encoding on LAD [3:0] from the host. Single, Demand, Verify, and Increment modes are
supported on the LPC interface.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock
source for these three counters.
The C600 chipset provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt controllers
are cascaded so that 14 external and two internal interrupts are possible. In addition, the C600
chipset supports a serial interrupt scheme.
3.3.10
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in
the previous section, the C600 incorporates the Advanced Programmable Interrupt Controller
(APIC).
3.3.11
Universal Serial Bus (USB) Controller
The C600 chipset has up to two Enhanced Host Controller Interface (EHCI) host controllers that
support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s
which is 40 times faster than full-speed USB. The C600 chipset supports up to fourteen USB 2.0
ports. All fourteen ports are high-speed, full-speed, and low-speed capable.
3.3.12
Gigabit Ethernet Controller
The Gigabit Ethernet Controller provides a system interface using a PCI function. The controller
provides a full memory-mapped or IO mapped interface along with a 64 bit address master
support for systems using more than 4 GB of physical memory and DMA (Direct Memory
Addressing) mechanisms for high performance data transfers. Its bus master capabilities enable
the component to process high-level commands and perform multiple operations; this lowers
processor utilization by off-loading communication tasks from the processor. Two large