Technical Product Specification

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Intel

Server Board S1400FP

Intel order number G64246-003

Revision 2.0

December, 2013

Platform Collaboration and Systems Division – Marketing

Summary of content (162 pages)

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Intel® Server Board S1400FP Technical Product Specification Intel order number G64246-003 Revision 2.
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Revision History Intel® Server Board S1400FP TPS Revision History Date July 2012 Revision Number 1.0 Initial release. October 2012 1.1 • Updated Table 1. • Correct errors in Table 2. • Updated Appendix E. December 2013 ii 2.0 Modifications ® ® Added support for Intel Xeon processor E5-2400 v2 product family Intel order number G64246-003 Revision 2.
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Intel® Server Board S1400FP TPS Disclaimers Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Table of Contents Intel® Server Board S1400FP TPS Table of Contents 1. Introduction ........................................................................................................................1 1.1 Chapter Outline ......................................................................................................1 1.2 Server Board Use Disclaimer .................................................................................1 2. Overview .....................................................
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Intel® Server Board S1400FP TPS Table of Contents 3.3.23 On-board Serial Attached SCSI (SAS)/Serial ATA (SATA) Support and Options.. 34 3.4 Integrated Baseboard Management Controller (BMC) Overview .......................... 36 3.4.1 Super I/O Controller .............................................................................................37 3.4.2 Graphics Controller and Video Support ................................................................38 3.4.3 Baseboard Management Controller ..........
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Table of Contents Intel® Server Board S1400FP TPS 6.11.9 Memory Thermal Throttling ..................................................................................61 6.12 Messaging Interfaces ...........................................................................................62 6.12.1 User Model ...........................................................................................................63 6.12.2 IPMB Communication Interface ..........................................................
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Intel® Server Board S1400FP TPS Table of Contents 8.3.8 SATA SGPIO Header ...........................................................................................87 8.3.9 SAS SGPIO Header .............................................................................................87 8.3.10 IPMB Connector ...................................................................................................87 8.4 Front Panel Connector .........................................................................
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Table of Contents Intel® Server Board S1400FP TPS 12.1.6 Capacitive Loading .............................................................................................106 12.1.7 Grounding ..........................................................................................................106 12.1.8 Residual Volatge Immunity in Standy mode ....................................................... 106 12.1.9 Common Mode Noise..............................................................................
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Intel® Server Board S1400FP TPS List of Figures List of Figures Figure 1. Intel® Server Board S1400FP Layout (S1400FP4 as shown) .......................................4 Figure 2. Intel® Server Board S1400FP Layout ...........................................................................5 Figure 3. Intel® Server Board S1400FP – Mounting Hole Locations (1 of 2) ................................7 Figure 4. Intel® Server Board S1400FP – Mounting Hole Locations (2 of 2) ................................
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List of Tables Intel® Server Board S1400FP TPS List of Tables Table 1. Intel® Server Board S1400FP Feature Set.....................................................................2 Table 2. Intel® Server Board S1400FP Component Layout .........................................................5 Table 3. UDIMM Support Guidelines .........................................................................................19 Table 4. RDIMM Support Guidelines ........................................................
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Intel® Server Board S1400FP TPS List of Tables Table 40. SATA Connector Pin-out ...........................................................................................90 Table 41. SAS Connector Pin-out .............................................................................................90 Table 42. External DB9 Serial A Port Pin-out ............................................................................91 Table 43. Internal 9-pin Serial B Header Pin-out ...................................
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List of Tables Intel® Server Board S1400FP TPS xii Intel order number G64246-003 Revision 2.
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Intel® Server Board S1400FP TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of the Intel® Server Board S1400FP. In addition, you can obtain design-level information for specific subsystems by ordering the External Product Specifications (EPS) or External Design Specifications (EDS) for a given subsystem.
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Overview 2. Intel® Server Board S1400FP TPS Overview The Intel® Server Board S1400FP is monolithic printed circuit boards (PCBs) with features designed to support the pedestal and rack server markets. 2.1 Intel® Server Boards S1400FP Feature Set ® Table 1.
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Intel® Server Board S1400FP TPS Feature     Overview Description One internal Type-A USB 2.0 port. One 9 pin USB header for eUSB SSD. ® One 1x7 pin header for optional Intel Local Control Panel support. One 30-pin front panel connector. Video Support  Integrated 2D video controller.  Dual monitor video mode is supported.  16 MB DDR3 Memory. LAN Two Gigabit Ethernet Ports through the Intel Ethernet Controller I350 (for S1400FP2).
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Overview 2.2 Intel® Server Board S1400FP TPS Server Board Layout ® Figure 1. Intel Server Board S1400FP Layout (S1400FP4 as shown) 4 Intel order number G64246-003 Revision 2.
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Intel® Server Board S1400FP TPS 2.2.1 Overview Server Board Connector and Component Layout The following figure shows the layout of the server board. Each connector and major component is identified by a number or letter, and a description is given in the figure below: ® Figure 2. Intel Server Board S1400FP Layout ® Table 2.
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Overview Intel® Server Board S1400FP TPS Description Description K Identify LED AI BMC Force Update jumper L Diagnostic LED AJ BIOS Default jumper M NIC 3/4 connectors (for S1400FP4 only) AK ME force update jumper N NIC 1/2 and USB 0/1/2/3 connectors AL Internal USB header O VGA connector AM Internal USB header P Serial B connector AN SATA SGPIO header Q Auxiliary Signal Power connector AO SATA Port 0/1 R System Fan 4 header AP SATA Port 2/3/4/5 S DIMM slots AQ SAS SGPI
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Intel® Server Board S1400FP TPS 2.2.2 Overview Server Board Mechanical Drawings ® Figure 3. Intel Server Board S1400FP – Mounting Hole Locations (1 of 2) Revision 2.
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Overview Intel® Server Board S1400FP TPS ® Figure 4. Intel Server Board S1400FP – Mounting Hole Locations (2 of 2) 8 Intel order number G64246-003 Revision 2.
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Intel® Server Board S1400FP TPS Overview ® Figure 5. Intel Server Boards S1400FP – Major Connector Pin-1 Locations (1 of 2) Revision 2.
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Overview Intel® Server Board S1400FP TPS ® Figure 6. Intel Server Boards S1400FP – Major Connector Pin-1 Locations (2 of 2) 10 Intel order number G64246-003 Revision 2.
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Intel® Server Board S1400FP TPS Overview ® Figure 7. Intel Server Boards S1400FP – Primary Side Keepout Zone Revision 2.
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Overview Intel® Server Board S1400FP TPS ® Figure 8. Intel Server Boards S1400FP – Primary Side Card Side Keepout Zone ® Figure 9. Intel Server Boards S1400FP – Primary Side Air Duct Keepout Zone 12 Intel order number G64246-003 Revision 2.
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Intel® Server Board S1400FP TPS Overview ® Figure 10. Intel Server Boards S1400FP – Second Side Keepout Zone Revision 2.
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Overview 2.2.3 Intel® Server Board S1400FP TPS Server Board Rear I/O Layout The following drawing shows the layout of the rear I/O components for the server board. A Serial Port A E NIC Port 3 (top)/NIC Port 4 (bottom), for S1400FP4 only B Video Port F Diagnostic LEDs C NIC Port 1/USB 0-1 G ID LED D NIC Port 2/USB 2-3 H System Status LED ® Figure 11. Intel Server Boards S1400FP Rear I/O Layout 14 Intel order number G64246-003 Revision 2.
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Intel® Server Board S1400FP TPS 3. Functional Architecture Functional Architecture The architecture and design of the Intel® Server Board S1400FP is based on the Intel® C600 chipset. The chipset is designed for systems based on the Intel® Xeon® processor in an FC-LGA 1356 Socket B2 package with Intel® QuickPath Interconnect (Intel® QPI). This chapter provides a high-level description of the functionality associated with each chipset component and the architectural blocks that make up the server boards.
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Functional Architecture 3.1 Intel® Server Board S1400FP TPS Processor Support The Intel® Server Board S1400FP includes one Socket-B2 (LGA-1356) processor socket and can support the following processor:   Intel® Xeon® processor E5-2400 product family, with a Thermal Design Power (TDP) of up to 95W. Intel® Xeon® processor E5-2400 v2 product family, with a Thermal Design Power (TDP) of up to 95W.
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Intel® Server Board S1400FP TPS 3.2 Functional Architecture Processor Function Overview With the release of the Intel® Xeon® processor E5-2400 product family, several key system components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module (IIO), have been combined into a single processor package and feature per socket; One Intel® QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 24 lanes of Gen 3 PCI Express* links capable of 8.
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Functional Architecture 3.2.1 Intel® Server Board S1400FP TPS Intel® QuickPath Interconnect The Intel® QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used in the processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency.
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Intel® Server Board S1400FP TPS Functional Architecture DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device. Independent channel mode supports x4 SDDC.
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Functional Architecture Intel® Server Board S1400FP TPS Table 4. RDIMM Support Guidelines Ranks Per DIMM and Data Width Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per Channel (DPC)2,3 Memory Capacity Per DIMM1 1 Slot per Channel 2 Slots per Channel 1DPC 1.35V SRx8 1GB 2GB 4GB 1066 1333 DRx8 2GB 4GB 8GB 1066 1333 SRx4 2GB 4GB 8GB 1066 1333 DRx4 4GB 8GB 16GB 1066 1333 1DPC 1.5V 1066 1333 1600 1066 1333 1600 1066 1333 1600 1066 1333 1600 2DPC 1.35V 1.
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Intel® Server Board S1400FP TPS Functional Architecture ® Figure 14. Intel Server Board S1400FP DIMM Slot Layout The following are generic DIMM population requirements that generally apply to the Intel® Server Board S1400FP.  All DIMMs must be DDR3 DIMMs • Registered DIMMs must be ECC only; unbuffered DIMMs can be ECC or non-ECC. However, Intel only validates and supports ECC memory for its server products. Mixing of Registered and Unbuffered DIMMs is not allowed per platform.
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Functional Architecture Intel® Server Board S1400FP TPS  When one DIMM is used, it must be populated in the BLUE DIMM slot (farthest away from the CPU) of a given channel.  When single and dual rank DIMMs are populated for 2DPC, always populate the higher number rank DIMM first (starting from the farthest slot), for example, first dual rank, and then single rank DIMM.
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Intel® Server Board S1400FP TPS Functional Architecture Regardless of RAS mode, the requirements for populating within a channel given in the section 3.2.2.2 must be met at all times. Note that support of RAS modes that require matching DIMM population between channels (Mirrored and Lockstep) require that ECC DIMMs be populated. Independent Channel Mode is the only mode that supports non-ECC DIMMs in addition to ECC DIMMs.
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Functional Architecture Intel® Server Board S1400FP TPS The correctable error that triggered the SFO may be logged to the BMC SEL, if it was the first one to occur in the system. That first correctable error event will be the only one logged for the system. However, since each channel is a Sparing Domain, the correctable error counting continues for other channels which are still in a redundant state. There can be as many SFO Events as there are memory channels with DIMMs installed. 3.2.2.4.
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Intel® Server Board S1400FP TPS Functional Architecture Lockstep channels must be populated identically. That is, each DIMM in one channel must have a corresponding DIMM of identical organization (number ranks, number banks, number rows, number columns). DIMMs may be of different speed grades, but the iMC module will be configured to operate all DIMMs according to the slowest parameters present by the Memory Reference Code (MRC). Performance in lockstep mode cannot be as high as with independent channels.
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Functional Architecture Intel® Server Board S1400FP TPS of the counting registers. This prevents correctable error counts from building up over an extended runtime. The correctable memory error threshold value is a configurable option in the BIOS Setup Utility, where you can configure it for 20/10/5/ALL/None.
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Intel® Server Board S1400FP TPS Functional Architecture  Non Transparent Bridge: PCI Express* non-transparent bridge (NTB) acts as a gateway that enables high performance, low overhead communication between two intelligent subsystems; the local and the remote subsystems.
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Functional Architecture 3.2.3.1 Intel® Server Board S1400FP TPS Network Interface Network connectivity is provided by means of one onboard Intel® Ethernet Controller I350 providing up to four 10/100/1000 Mb Ethernet ports. The NIC chip is supported by implementing x2 PCIe Gen2 signals from the Intel® C600 PCH. On the Intel® Server Board S1400FP, two for S1400FP2 and four for S1400FP4 external 10/100/1000 Mb RJ45 Ethernet ports are provided.
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Intel® Server Board S1400FP TPS Functional Architecture On the Intel® Server Boards S1400FP, the chipset provides support for the following on-board functions:  Digital Media Interface (DMI)   PCI Express* Interface Serial ATA (SATA) Controller  Serial Attached SCSI (SAS)/SATA Controller  AHCI   Rapid Storage Technology PCI Interface  Low Pin Count (LPC) interface  Serial Peripheral Interface (SPI)   Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) Adv
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Functional Architecture 3.3.3 Intel® Server Board S1400FP TPS Serial ATA (SATA) Controller The C600 chipset has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s (600 MB/s) on up to two ports (Port 0 and 1 Only) while all ports support rates up to 3.0 Gb/s (300 MB/s) and up to 1.5 Gb/s (150 MB/s).
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Intel® Server Board S1400FP TPS 3.3.8 Functional Architecture Serial Peripheral Interface (SPI) The C600 chipset implements an SPI Interface as an alternative interface for the BIOS flash device. An SPI flash device can be used as a replacement for the FWH, and is required to support Gigabit Ethernet and Intel® Active Management Technology. The C600 chipset supports up to two SPI flash devices with speeds up to 50 MHz, utilizing two chip select pins. 3.3.
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Functional Architecture Intel® Server Board S1400FP TPS configurable transmit and receive FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS). The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification.
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Intel® Server Board S1400FP TPS Functional Architecture  Function Disable. The chipset provides the ability to disable the following integrated functions: LAN, USB, LPC, SATA, PCI Express* or SMBus*. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disabled functions.  Intruder Detect.
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Functional Architecture Intel® Server Board S1400FP TPS allows system manufacturers to improve efficiency by using industry available tools to test the C600 chipset on an assembled board. Since JTAG is a serial interface, it eliminates the need to create probe points for every pin in an XOR chain. This eases pin breakout and trace routing and simplifies the interface between the system and a bed-of-nails tester. 3.3.
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Intel® Server Board S1400FP TPS Product Code Color Functional Architecture On-Server Board SATA/SAS Capable Controller On-Server Board AHCI Capable SATA Controller ® Intel RSTE SATA R0,1,10,5 ® or Intel ESRT2 SATA R0,1,10 ® Intel RSTE SATA R0,1,10,5 ® or Intel ESRT2 SATA R0,1,10,5 ® Intel RSTE SATA R0,1,10,5 ® or Intel ESRT2 SATA R0,1,10 ® Intel RSTE SATA R0,1,10,5 ® or Intel ESRT2 SATA R0,1,10,5 ® Intel RSTE SATA R0,1,10,5 ® or Intel ESRT2 SATA R0,1,10 ® Intel RSTE SATA R0,1,10,5 ® or Inte
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Functional Architecture   Intel® Server Board S1400FP TPS OS Support = Microsoft Windows 7*, Microsoft Windows 2008*, Microsoft Windows 2003*, RHEL*, SLES*, other Linux* variants using partial source builds. Utilities = Microsoft Windows* GUI and CLI, Linux* GUI and CLI, DOS CLI, and EFI CLI. 3.3.23.2 Intel® Rapid Storage Technology (RSTe) Features of the embedded software RAID option Intel® Rapid Storage Technology (RSTe) include the following:         3.
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Intel® Server Board S1400FP TPS Functional Architecture Figure 17. Integrated Baseboard Management Controller (BMC) Overview Figure 18. Integrated BMC Hardware 3.4.
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Functional Architecture 3.4.1.1 Intel® Server Board S1400FP TPS Keyboard and Mouse Support The server board does not support PS/2 interface keyboard and mouse. However, the system BIOS recognizes the USB specification-compliant keyboard and mouse. 3.4.1.2 Wake-up Control The super I/O contains functionality that allows various events to power on and power off the system. 3.4.
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Intel® Server Board S1400FP TPS Functional Architecture Table 9. Video mode On-board Video Enabled Disabled Dual Monitor Video Enabled Disabled 3.4.3 Shaded if on-board video is set to "Disabled" Baseboard Management Controller The server board utilizes the following features of the embedded baseboard management controller.  IPMI 2.
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Functional Architecture Intel® Server Board S1400FP TPS  Hardware based Video Compression and Redirection Logic  Supports both text and Graphics redirection  Hardware assisted Video redirection using the Frame Processing Engine  Direct interface to the Integrated Graphics Controller registers and Frame buffer  Hardware based encryption engine 3.4.3.2 Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10/100 network interfaces.
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Intel® Server Board S1400FP TPS System Security 4. System Security 4.1 BIOS Password Protection The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords can restrict entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress automatic USB device reordering. There is also an option to require a Power On password entry to boot the system.
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System Security Intel® Server Board S1400FP TPS In addition to restricting access to most Setup fields to viewing only when a User password is entered, defining a User password imposes restrictions on booting the system. To simply boot in the defined boot order, no password is required. However, the F6 Boot popup prompts for a password, and can only be used with the Administrator password.
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Intel® Server Board S1400FP TPS     System Security Produces EFI and legacy interfaces to a TPM-enabled operating system for using TPM. Produces ACPI TPM device and methods to allow a TPM-enabled operating system to send TPM administrative command requests to the BIOS. Verifies operator physical presence. Confirms and executes operating system TPM administrative command requests. Provides BIOS Setup options to change TPM security states and to clear TPM ownership.
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System Security 4.2.3.1 Intel® Server Board S1400FP TPS Security Screen To enter the BIOS Setup, press the F2 function key during boot time when the OEM or Intel® logo displays. The following message displays on the diagnostics screen and under the Quiet Boot logo screen: Press to enter setup When the Setup is entered, the Main screen is displayed.
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Intel® Server Board S1400FP TPS System Security Table 10. TPM Setup Utility – Security Configuration Screen Fields Setup Item TPM State* Options Enabled and Activated Enabled and Deactivated Disabled and Activated Disabled and Deactivated Help Text Comments Information only. Shows the current TPM device state. A disabled TPM device will not execute commands that use TPM functions and TPM security operations will not be available.
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System Security Intel® Server Board S1400FP TPS Technology compatible measured launched environment (MLE). The MLE consists of a virtual machine monitor, an OS or an application. In addition, Intel® Trusted Execution Technology requires the system to include a TPM v1.2, as defined by the Trusted Computing Group TPM PC Client Specification, Revision 1.2. When available, Intel Trusted Execution Technology can be enabled or disabled in the processor from a BIOS Setup option.
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Intel® Server Board S1400FP TPS Technology Support 5. Technology Support 5.1 Intel® Trusted Execution Technology The Intel® Xeon® Processor E5 4600/2600/2400/1600 Product Families support Intel® Trusted Execution Technology (Intel® TXT), which is a robust security environment designed to help protect against software-based attacks. Intel® Trusted Execution Technology integrates new security features and capabilities into the processor, chipset, and other platform components.
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Technology Support Intel® Server Board S1400FP TPS For more information on the DMAR table and the DRHD entry format, refer to the Intel® Virtualization Technology for Directed I/O Architecture Specification. For more general information about VT-x, VT-d, and VT-c, a good reference is Enabling Intel® Virtualization Technology Features and Benefits White Paper. 5.
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Intel® Server Board S1400FP TPS Technology Support code used by OS-Directed Power Management (OSPM) for negotiating processor P and T state changes for power limiting. PMBus* compliant power supplies provide the capability to monitoring input power consumption, which is necessary to support NM. Below are the some of the applications of Intel® Intelligent Power Node Manager technology.
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Platform Management Functional Overview 6. Intel® Server Board S1400FP TPS Platform Management Functional Overview Platform management functionality is supported by several hardware and software components integrated on the server board that work together to control system functions, monitor and report system health, and control various thermal and performance features to maintain (when possible) server functionality in the event of component failure and/or environmentally stressed conditions.
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Intel® Server Board S1400FP TPS Platform Management Functional Overview See also the Intelligent Platform Management Interface Specification Second Generation v2.0. 6.1.2 Non IPMI Features The BMC supports the following non-IPMI features.   In-circuit BMC firmware update BMC FW reliability enhancements: o Redundant BMC boot blocks to avoid possibility of a corrupted boot block resulting in a scenario that prevents a user from updating the BMC.
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Platform Management Functional Overview                   6.1.3 Intel® Server Board S1400FP TPS Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported on embedded NICs). Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on embedded NICs). E-mail alerting Embedded web server o Support for embedded web server UI in Basic Manageability feature set.
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Intel® Server Board S1400FP TPS                     DCMI 1.1 compliance (product-specific). Support for embedded web server UI in Basic Manageability feature set. Enhancements to embedded web server o Human-readable SEL o Additional system configurability o o Additional system monitoring capability Enhanced on-line help Enhancements to KVM redirection o Support for higher resolution Support for EU Lot6 compliance Management support for PMBus* rev1.
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Platform Management Functional Overview Feature Diagnostic Beep Code Support X X Power State Retention X X ARP/DHCP Support X X PECI Thermal Management Support X X E-mail Alerting X X Embedded Web Server X X SSH Support X X Advanced X Integrated Remote Media Redirection X X X Intel Intelligent Power Node Manager Support X X SMASH CLP X X ® 6.3.1 Basic Integrated KVM Lightweight Directory Access Protocol (LDAP) 6.
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Intel® Server Board S1400FP TPS  Platform Management Functional Overview Secondary Service Processor (SSP), which provides the HW capability of offloading time critical processing tasks from the main ARM core. Emulex* Pilot III contains an integrated SIO, KVMS subsystem and graphics controller with the following features: 6.4 Advanced Configuration and Power Interface (ACPI) The server board has support for the following ACPI states: Table 13.
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Platform Management Functional Overview Source Chipset External Signal Name or Internal Subsystem Sleep S4/S5 signal (same as POWER_ON) Intel® Server Board S1400FP TPS Capabilities Turns power on or off CPU Thermal CPU Thermtrip Turns power off WOL (Wake On LAN) LAN Turns power on 6.6 BMC Watchdog The BMC FW is increasingly called upon to perform system functions that are time-critical; failure to provide these functions in a timely manner can result in system or component damage.
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Intel® Server Board S1400FP TPS Platform Management Functional Overview After the BIOS has identified and saved the BSP information, it sets the FRB2 timer use bit and loads the watchdog timer with the new timeout interval. If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC (if so configured) logs a watchdog expiration event showing the FRB2 timeout in the event data bytes. The BMC then hard resets the system, assuming the BIOS-selected reset as the watchdog timeout action.
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Platform Management Functional Overview Intel® Server Board S1400FP TPS 6.10 System Event Log (SEL) The BMC implements the system event log as specified in the Intelligent Platform Management Interface Specification, Version 2.0. The SEL is accessible regardless of the system power state through the BMC's in-band and out-of-band interfaces. The BMC allocates 65,502 bytes (approximately 64 KB) of non-volatile storage space to store system events. The SEL timestamps may not be in order.
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Intel® Server Board S1400FP TPS 6.11.2 Platform Management Functional Overview Setting Throttling Mode Select the most appropriate memory thermal throttling mechanism for memory sub-system from [Auto], [DCLTT], [SCLTT], and [SOLTT].  [Auto] – BIOS automatically detect and identify the appropriate thermal throttling mechanism based on DIMM type, airflow input, DIMM sensor availability.
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Platform Management Functional Overview 6.11.7 Intel® Server Board S1400FP TPS Fan Profiles The server system supports multiple fan control profiles to support acoustic targets and American Society of Heating, Refrigerating, and Air Conditioning Engineers (ASHRAE) compliance. The BIOS Setup utility can be used to choose between meeting the target acoustic level or enhanced system performance. This is accomplished through fan profiles. The BMC supports eight fan profiles, numbered from 0 to 7. Table 15.
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Intel® Server Board S1400FP TPS        Note: 1. 2. 3. 4. 5. 6. 7. 8. 9.
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Platform Management Functional Overview Intel® Server Board S1400FP TPS levels are changed dynamically to cap throttling based on memory and system thermal conditions as determined by the system and DIMM power and thermal parameters. The BMC’s fan speed control functionality is linked to the memory throttling mechanism used.
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Intel® Server Board S1400FP TPS Platform Management Functional Overview Channel ID 8– 0Dh 0Eh 0Fh Notes: 1. 2. 6.12.1 Interface Reserved 2 Self SMS/Receive Message Queue Supports Sessions – – No Optional hardware supported by the server system. Refers to the actual channel used to send the request. User Model The BMC supports the IPMI 2.0 user model. 15 user IDs are supported. These 15 users can be assigned to any channel. The following restrictions are placed on user-related operations: 1.
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Platform Management Functional Overview 6.12.3.2 Intel® Server Board S1400FP TPS BMC LAN Channels The BMC supports three RMII/RGMII ports that can be used for communicating with Ethernet devices. Two ports are used for communication with the on-board NICs and one is used for communication with an Ethernet PHY located on an optional RMM4 add-in module. 6.12.3.2.1 Baseboard NICs The on-board Ethernet controller provides support for a Network Controller Sideband Interface (NC-SI) manageability interface.
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Intel® Server Board S1400FP TPS Platform Management Functional Overview MAC addresses are assigned for management NICs from a pool of up to 3 MAC addresses allocated specifically for manageability. The Intel® Server Board S1400FP4 has seven MAC addresses programmed at the factory.
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Platform Management Functional Overview Intel® Server Board S1400FP TPS The BMC supports IPv4 and IPv6 simultaneously, so they are both configured separately and completely independently. For example, IPv4 can be DHCP configured while IPv6 is statically configured or vice versa. The parameters for IPv6 are similar to the parameters for IPv4 with the following differences:  An IPv6 address is 16 bytes versus 4 bytes for IPv4.  An IPv6 prefix is 0 to 128 bits whereas IPv4 has a 4 byte subnet mask.
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Intel® Server Board S1400FP TPS Platform Management Functional Overview The LAN Failover enable/disable command may be sent at any time. After it has been enabled, standard IPMI commands for setting channel configuration that specify a LAN channel other than the first will return an error code. 6.12.3.5 BMC IP Address Configuration Enabling the BMC’s network interfaces requires using the Set LAN Configuration Parameter command to configure LAN configuration parameter 4, IP Address Source.
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Platform Management Functional Overview Intel® Server Board S1400FP TPS 2. The user may only set a default gateway address that can potentially exist within the subnet specified above. Default gateway addresses outside the BMC’s subnet are technically unreachable and the BMC will not set the default gateway address to an unreachable value. The BMC returns a 0xCC (Invalid Data Field in Request) completion code for default gateway addresses outside its subnet. 3.
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Intel® Server Board S1400FP TPS           Platform Management Functional Overview DHCP Hostname can be set regardless of the IP Address source configured on the BMC. But this parameter is only used if the IP Address source is set to DHCP. When Byte 2 is set to “Update in progress”, all the 16 Block Data Bytes (Bytes 3 – 18) must be present in the request. When Block Size < 16, it must be the last Block request in this series.
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Platform Management Functional Overview Intel® Server Board S1400FP TPS by means of parameter 20 of the Set LAN Config Parameters IPMI command. When a VLAN ID is configured and enabled, the BMC only accepts packets with that VLAN tag/ID. Conversely, all BMC generated LAN packets on the channel include the given VLAN tag/ID. Valid VLAN IDs are 1 through 4094, VLAN IDs of 0 and 4095 are reserved, per the 802.1Q VLAN Specification. Only one VLAN can be enabled at any point in time on a LAN channel.
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Intel® Server Board S1400FP TPS 6.12.9 Platform Management Functional Overview Platform Event Filter (PEF) The BMC includes the ability to generate a selectable action, such as a system power-off or reset, when a match occurs to one of a configurable set of events. This capability is called Platform Event Filtering, or PEF. One of the available PEF actions is to trigger the BMC to send a LAN alert to one or more destinations. The BMC supports 20 PEF filters.
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Platform Management Functional Overview 6.12.11 Intel® Server Board S1400FP TPS Alert Policy Table Associated with each PEF entry is an alert policy that determines which IPMI channel the alert is to be sent. There is a maximum of 20 alert policy entries. There are no pre-configured entries in the alert policy table because the destination types and alerts may vary by user. Each entry in the alert policy table contains four bytes for a maximum table size of 80 bytes. 6.12.11.
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Intel® Server Board S1400FP TPS 6.12.13 Platform Management Functional Overview Embedded Web Server BMC Base manageability provides an embedded web server and an OEM-customizable web GUI which exposes the manageability features of the BMC base feature set. It is supported over all on-board NICs that have management connectivity to the BMC as well as an optional RMM4 dedicated add-in management NIC. At least two concurrent web sessions from up to two different users is supported.
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Platform Management Functional Overview              Embedded Platform Debug feature - Allow the user to initiate a “diagnostic dump” to a file that can be sent to Intel for debug purposes. Virtual Front Panel. The Virtual Front Panel provides the same functionality as the local front panel. The displayed LEDs match the current state of the local panel LEDs. The displayed buttons (for example, power button) can be used in the same manner as the local buttons.
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Intel® Server Board S1400FP TPS     Platform Management Functional Overview Note that the chassis ID will turn on because of the original chassis ID button press and will reflect in the Virtual Front Panel after VFP sync with BMC. Virtual Front Panel will not reflect the chassis LED software blinking from the software command as there is no mechanism to get the chassis ID Led status.
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Platform Management Functional Overview Intel® Server Board S1400FP TPS gets this data from the power supplies from the PMBus* manufacturer-specific commands. o    Storage of system identification in power supply. The BMC copies board and system serial numbers and part numbers into the power supply whenever a new power supply is installed in the system or when the system is first powered on. This information is included as part of the power supply black box data for each installed power supply.
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Intel® Server Board S1400FP TPS Platform Management Functional Overview Category Data Memory Map (EFI and Legacy) for current boot Table 19. Additional Diagnostics on Error Category System Data 6.12.
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Advanced Management Feature Support (RMM4) 7. Intel® Server Board S1400FP TPS Advanced Management Feature Support (RMM4) The integrated baseboard management controller has support for advanced management features which are enabled when an optional Intel® Remote Management Module 4 (RMM4) is installed. RMM4 is comprised of two boards – RMM4 lite and the optional Dedicated Server Management NIC (DMN). Table 20.
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Intel® Server Board S1400FP TPS Advanced Management Feature Support (RMM4) ® Figure 22. Intel RMM4 Dedicated Management NIC Installation If the optional Dedicated Server Management NIC is not used then the traffic can only go through the onboard Integrated BMC-shared NIC and will share network bandwidth with the host system. Advanced manageability features are supported over all NIC ports enabled for server manageability. 7.
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Advanced Management Feature Support (RMM4) Intel® Server Board S1400FP TPS KVM redirection includes a “soft keyboard” function. The “soft keyboard” is used to simulate an entire keyboard that is connected to the remote system. The “soft keyboard” functionality supports the following layouts: English, Dutch, French, German, Italian, Russian, and Spanish.
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Intel® Server Board S1400FP TPS Advanced Management Feature Support (RMM4) The redirection of KVM over IP is performed in parallel with the local KVM without affecting the local KVM operation. 7.1.3 Security The KVM redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual algorithm that is used is negotiated with the client based on the client’s capabilities. 7.1.
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Advanced Management Feature Support (RMM4) Intel® Server Board S1400FP TPS  The media redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual algorithm that is used is negotiated with the client based on the client’s capabilities.  A remote media session is maintained even when the server is powered-off (in standby mode). No restart of the remote media session is required during a server reset or power on/off.
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Intel® Server Board S1400FP TPS 8. On-board Connector/Header Overview On-board Connector/Header Overview The following section provides detailed information regarding all connectors, headers, and jumpers on the server boards. 8.1 Board Connector Information The following table lists all connector types available on the board and the corresponding preference designators printed on the silkscreen. Table 21.
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On-board Connector/Header Overview Connector Intel® Server Board S1400FP TPS Quantity Reference Designators Connector Type Pin Count LCP 1 J4J4 Header 7 IPMB 1 J3J8 Header 4 Configuration jumpers 5 J3J2 (Force Integrated BMC update), J3J5 (Password Clear), J3J4 (BIOS Recovery), J3J1 (Reset BIOS Configuration) J3J3 (ME Firmware Update) Jumper 3 TPM 1 J5J1 Connector 14 Chassis Intrusion 1 J3J10 Header 2 8.
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Intel® Server Board S1400FP TPS On-board Connector/Header Overview Pin 8 Signal +12 Vdc DDR3_CPU1 Color Yellow/black Table 24. Power Supply Auxiliary Signal Connector Pin-out Pin 1 2 3 4 5 8.3 Signal SMB_CLK_FP_PWR_R SMB_DAT_FP_PWR_R SMB_ALRT_3_ESB_R 3.3 V SENSE3.3 V SENSE+ Color Orange Black Red Yellow Green System Management Headers 8.3.
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On-board Connector/Header Overview 8.3.2 Intel® Server Board S1400FP TPS TPM connector Table 27. TPM connector Pin-out Pin 1 3 5 7 9 11 13 8.3.3 Signal Name No pin LPC_LAD<0> IRQ_SERIAL P3V3 RST_IBMC_NIC_N LPC_LAD<3> GND Pin 2 4 6 8 10 12 14 Signal Name LPC_LAD<1> GND LPC_FRAME_N GND CLK_33M_TPM_CONN GND LPC_LAD<2> Intel® RAID C600 Upgrade Key Connector The server board provides one connector to support Intel® RAID C600 Upgrade Key.
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Intel® Server Board S1400FP TPS 8.3.7 On-board Connector/Header Overview Chassis Intrusion Header The server board includes a 2-pin chassis intrusion header which can be used when the chassis is configured with a chassis intrusion switch. The header has the following pin-out: Table 32. Chassis Intrusion Header Pin-out Header State Pins 1 and 2 closed Pins 1 and 2 open 8.3.8 Description FM_INTRUDER_HDR_N is pulled HIGH. Chassis cover is closed. FM_INTRUDER_HDR_N is pulled LOW. Chassis cover is removed.
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On-board Connector/Header Overview Intel® Server Board S1400FP TPS The following table provides the pin-out for this connector: Table 36. Front Panel 30-pin Connector Pin-out 8.4.1 Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 Signal SB3.3V Key Power LED Cathode 3.3V HDD Activity LED Cathode Power Switch GND (Power Switch) Reset Switch GND (Reset/ID/NMI Switch) System ID Switch Pull Down NMI to CPU Switch Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 Signal SB3.
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Intel® Server Board S1400FP TPS 8.4.4 On-board Connector/Header Overview NMI Button Support When the NMI button is pressed, it puts the server in a halt state and causes the BMC to issue a non-maskable interrupt (NMI). This can be useful when performing diagnostics for a given issue where a memory download is necessary to help determine the cause of the problem. Once an NMI has been generated by the BMC, the BMC does not generate another NMI until the system has been reset or powered down.
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On-board Connector/Header Overview 8.5 8.5.1 Intel® Server Board S1400FP TPS I/O Connectors VGA Connector The following table details the pin-out definition of the VGA connector. Table 39. VGA Connector Pin-out Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 8.5.
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Intel® Server Board S1400FP TPS 8.5.3 On-board Connector/Header Overview Serial Port Connectors The server board provides one external DB9 Serial A port and one internal 9-pin Serial B header. The following tables define the pin-outs: Table 42.
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On-board Connector/Header Overview Intel® Server Board S1400FP TPS One low-profile 2x5 connector (J2E1) on the server boards provides an option to support a lowprofile USB Solid State Drive. Table 45.
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Intel® Server Board S1400FP TPS On-board Connector/Header Overview their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non-operating limits. Revision 2.
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Jumper Blocks 9. Intel® Server Board S1400FP TPS Jumper Blocks The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server boards. The following symbol identifies Pin 1 on each jumper block on the silkscreen: ▼ Figure 23. Jumper Blocks Note: 1. For safety purposes, the power cord should be disconnected from a system before removing any system components or moving any of the on-board jumper blocks. 2.
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Intel® Server Board S1400FP TPS Jumper Blocks Table 48. Server Board Jumpers Jumper Name J3J2: BMC Force Update Pins 1-2 System Results BMC Firmware Force Update Mode – Disabled (Default) 2-3 BMC Firmware Force Update Mode – Enabled J3J4: BIOS Recovery 1-2 Pins 1-2 should be jumpered for normal system operation. (Default) 2-3 The main system BIOS does not boot with pins 2-3 jumpered. The system only boots from EFI-bootable recovery media with a recovery BIOS image present.
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Jumper Blocks 9.2 Intel® Server Board S1400FP TPS Management Engine (ME) Firmware Force Update Jumper Block When the ME Firmware Force Update jumper is moved from its default position, the ME is forced to operate in a reduced minimal operating capacity. This jumper should only be used if the ME firmware has gotten corrupted and requires re-installation. The following procedure should be followed.
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Intel® Server Board S1400FP TPS 9.4 Jumper Blocks BIOS Default Jumper Block This jumper resets BIOS Setup options to their default factory settings. 1. Power down the server and unplug the power cords. 2. Move BIOS DFLT jumper from the default (pins 1 and 2) position to the Set BIOS Defaults position (pins 2 and 3). 3. Wait 5 seconds then move the jumper back to the default position of pins 1 and 2 4. Install Power Cords. 5. Power on system.
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Intel® Light Guided Diagnostics Intel® Server Board S1400FP TPS 10. Intel® Light Guided Diagnostics The server board includes several on-board LED indicators to aid troubleshooting various board level faults. The following diagram shows the location for each. Figure 23. On-Board LED Placement 10.1 System ID LED The server board includes a blue system ID LED which is used to visually identify a specific server installed among many other similar servers.
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Intel® Server Board S1400FP TPS Intel® Light Guided Diagnostics 10.2 System Status LED The server board includes a bi-color System Status LED. The System Status LED on the server board is tied directly to the System Status LED on the front panel (if present). This LED indicates the current health of the server. Possible LED states include solid green, blinking green, blinking amber, and solid amber.
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Intel® Light Guided Diagnostics Color State Intel® Server Board S1400FP TPS Criticality Amber Solid on Critical, nonrecoverable Off N/A Not ready Description 3. Minimum number of fans to cool the system not present or failed 4. Hard drive fault 5. Power Unit Redundancy sensor – Insufficient resources offset (indicates not enough power supplies present) 6.
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Intel® Server Board S1400FP TPS Intel® Light Guided Diagnostics 10.4 Post Code Diagnostic LEDs A bank of eight POST code diagnostic LEDs are located on the back edge of the server next to the stacked USB connectors. During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the given POST code to the POST code diagnostic LEDs.
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Environmental Limits Specification Intel® Server Board S1400FP TPS 11. Environmental Limits Specification The following table defines the Intel® Server Board S1400FP operating and non-operating environmental limits. Operation of the Intel® Server Board S1400FP at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 51.
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Intel® Server Board S1400FP TPS Environmental Limits Specification building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible, if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. 11.2 MTBF The following is the calculated Mean Time Between Failures (MTBF).
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Server Board Power Distribution Intel® Server Board S1400FP TPS 12. Server Board Power Distribution This section provides power supply design guidelines for a system using the Intel® Server Board S1400FP. The following diagram shows the power distribution implemented on this server board. Figure 24. Power Distribution Block Diagram The power supply data provided in this section is for reference purposes only.
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Intel® Server Board S1400FP TPS Server Board Power Distribution Table 53. Over Voltage Protection Limits Parameter 5V 12V1 12V2 3.3V Min − 12V 5Vstby Max. 0.3 0.7 1.5 0.5 10.0 16.0 16.0 18.0 0.0 0.5 0.0 2.5 Peak Unit A A A A 18.0 18.0 A 3.0 A Notes: 1. 2. 3. 4. 5. 12.1.2 Max combined power for all output shall not exceed 365W. Peak combined power for all outputs shall not exceed 385W. Max combined power of 12V1 and 12V2 shall not exceed 318W. Max combined power on 3.
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Server Board Power Distribution 12.1.5 Intel® Server Board S1400FP TPS Dynamic Loading The output voltages remain within limits specified for the step loading and capacitive loading specified in the table below. The load transient repetition rate is tested between 50Hz and 5kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The ∆ step load may occur anywhere within the MIN load to the MAX load conditions. Table 56.
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Intel® Server Board S1400FP TPS 12.1.9 Server Board Power Distribution Common Mode Noise The Common Mode noise on any output does not exceed 350mV pk-pk over the frequency band of 10Hz to 20MHz. The measurement is made across a 100Ω resistor between each of DC outputs, including ground at the DC power connector and chassis ground (power subsystem enclosure). The test set-up shall use a FET probe such as Tektronix model P6046 or equivalent. 12.1.
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Server Board Power Distribution Intel® Server Board S1400FP TPS Table 59. Output Voltage Timing Item Tvout_rise Tvout_on T vout_off Description Output voltage rise time from each main output. Output rise time for the 5Vstby output. All main outputs must be within regulation of each other within this time. All main outputs must leave regulation within this time. MIN 2 1 MAX 50 25 50 UNITS ms ms ms 400 ms Max. Units ms Vout V1 10% Vout V2 V3 V4 Tvout Tvout_off rise Tvout_on Figure 26.
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Intel® Server Board S1400FP TPS Item Tpwok_low Tsb_vout T5VSB_holdup Server Board Power Distribution Description Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal. Delay from 5VSB being in regulation to O/Ps being in regulation at AC turn on. Time the 5VSB output voltage stays within regulation after loss of AC. Min. Max.
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Appendix A: Integration and Usage Tips Intel® Server Board S1400FP TPS Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, you must remove AC power cord. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.
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Intel® Server Board S1400FP TPS Appendix B: Integrated BMC Sensor Tables Appendix B: Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.
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Appendix B: Integrated BMC Sensor Tables  Intel® Server Board S1400FP TPS Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states. You can rearm the sensors manually or automatically. This column indicates the type supported by the sensor.
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Intel® Server Board S1400FP TPS Appendix B: Integrated BMC Sensor Tables Table 61. Integrated BMC Core Sensors Full Sensor Name (Sensor name in SDR) Power Unit Status Sensor # 01h Platform Applicability All (Pwr Unit Status) Sensor Type Power Unit 09h Event/Reading Event Offset Triggers Type Sensor Specific 6Fh Contrib.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel® Server Board S1400FP TPS Sensor Type Event/Reading Event Offset Triggers Type Contrib. To System Status 06 – Redundant: degraded from fully redundant state. Degraded 07 – Redundant: Transition from non-redundant state.
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) Button Sensor (Button) BMC Watchdog Voltage Regulator Watchdog Sensor # 09h 0Ah 0Bh Platform Applicability All All All Appendix B: Integrated BMC Sensor Tables Sensor Type Button/Switch 14h (Fan Redundancy) Revision 2.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) SSB Thermal Trip (SSB Therm Trip) IO Module Presence (IO Mod Presence) SAS Module Presence (SAS Mod Presence) BMC Firmware Health (BMC FW Health) System Airflow (System Airflow) FW Update Status Sensor # 0Dh 0Eh 0Fh 10h Platform Applicability All Intel® Server Board S1400FP TPS Sensor Type Temperature 01h Platformspecific Module/Board Platformspecific Module/Board All 11h All 12h All 15h 15h Mgmt Health 28h
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) IO Module2 Presence (IO Mod2 Presence) Baseboard Temperature 5 (Platform Specific) Baseboard Temperature 6 (Platform Specific) IO Module2 Temperature Sensor # (PCI Riser 5 Temp) PCI Riser 4 Temperature (PCI Riser 4 Temp) Baseboard +1.05V Processor3 Vccp (BB +1.05Vccp P3) Revision 2.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard +1.
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) PCI Riser 1 Temperature (PCI Riser 1 Temp) IO Riser Temperature Sensor # Sensor Type Event/Reading Event Offset Triggers Type 27h Platformspecific Temperature Threshold 01h 01h 28h Platformspecific Temperature Threshold 01h 01h 29h Chassisspecific Temperature Threshold 01h 01h 2Ah Chassisspecific Temperature Threshold 01h 01h 2Bh Chassisspecific Temperature Threshold 01h 01h 2Ch Platformspecific Tempera
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Network Interface Controller Temperature Sensor # Platform Applicability 2Fh All 30h–3Fh Chassis and Platform Specific 40h–4Fh Chassis and Platform Specific Intel® Server Board S1400FP TPS Sensor Type Event/Reading Event Offset Triggers Type Temperature Threshold 01h 01h Fan Threshold 04h 01h Fan Generic 08h [u,l] [c,nc] (LAN NIC Temp) Fan Tachometer Sensors (Chassis specific sensor names) Fan Present Sensor
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) Power Supply 2 AC Power Input Sensor # Sensor Type Event/Reading Event Offset Triggers Type 55h Chassisspecific Other Units Threshold 0Bh 01h 58h Chassisspecific Current Threshold 03h 01h 59h Chassisspecific Current Threshold 03h 01h 5Ch Chassisspecific Temperature Threshold 01h 01h 5Dh Chassisspecific (PS2 Power In) Power Supply 1 +12V % of Maximum Current Output Platform Applicability Appendix B: Integrat
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel® Server Board S1400FP TPS Sensor Type Event/Reading Event Offset Triggers Type Contrib.
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) Processor 1 Thermal Control % Sensor # 78h Platform Applicability All (P1 Therm Ctrl %) Processor 2 Thermal Control % 79h All (P2 Therm Ctrl %) Processor 3 Thermal Control % 7Ah (P3 Therm Ctrl %) Processor 4 Thermal Control % 7Bh Platformspecific 7Ch All (P4 Therm Ctrl %) Processor 1 ERR2 Timeout Platformspecific (P1 ERR2) Processor 2 ERR2 Timeout 7Dh All (P2 ERR2) Processor 3 ERR2 Timeout 7Eh (P3 ERR2) Processor 4 E
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Catastrophic Error Sensor # 80h Platform Applicability All (CATERR) Processor1 MSID Mismatch (P1 MSID Mismatch) Processor Population Fault 81h 82h All All (CPU Missing) Processor 1 DTS Thermal Margin (P1 DTS Therm Mgn) Processor 2 DTS Thermal Margin (P2 DTS Therm Mgn) Processor 3 DTS Thermal Margin (P3 DTS Therm Mgn) Processor 4 DTS Thermal Margin (P4 DTS Therm Mgn) Processor2 MSID Mismatch (P2 MSID Mismatch) 124 83h
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) Processor 1 VRD Temperature Sensor # 90h Platform Applicability All Appendix B: Integrated BMC Sensor Tables Sensor Type Temperature 01h (P1 VRD Hot) Processor 2 VRD Temperature 91h All Temperature 01h (P2 VRD Hot) Processor 3 VRD Temperature 92h All Temperature 01h (P3 VRD Hot) Processor 4 VRD Temperature 93h All Temperature 01h (P4 VRD Hot) Processor 1 Memory VRD Hot 0-1 94h All (P1 Mem01 VRD Hot) Processor 1 Memor
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 2 Memory VRD Hot 2-3 Sensor # 97h Platform Applicability All (P2 Mem23 VRD Hot) Processor 3 Memory VRD Hot 0-1 98h All (P3 Mem01 VRD Hot) Processor 3 Memory VRD Hot 2-3 99h All (P4 Mem23 VRD Hot) Processor 4 Memory VRD Hot 0-1 9Ah All (P4 Mem01 VRD Hot) Processor 4 Memory VRD Hot 2-3 9Bh All (P4 Mem23 VRD Hot) Power Supply 1 Fan Tachometer 1 (PS1 Fan Tach 1) 126 A0h Chassisspecific Intel® Server Boa
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Appendix B: Integrated BMC Sensor Tables Sensor Type Power Supply 1 Fan Tachometer 2 (PS1 Fan Tach 2) A1h Chassisspecific Fan Power Supply 2 Fan Tachometer 1 (PS2 Fan Tach 1) A4h Chassisspecific Fan Power Supply 2 Fan Tachometer 2 (PS2 Fan Tach 2) A5h Chassisspecific Fan Processor 1 DIMM Aggregate Thermal Margin 1 04h 04h 04h Event/Reading Event Offset Triggers Type Contrib.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 2 DIMM Aggregate Thermal Margin 2 Sensor # Platform Applicability Intel® Server Board S1400FP TPS Sensor Type Event/Reading Event Offset Triggers Type Contrib.
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Processor 1 DIMM Thermal Trip C0h All (P1 Mem Thrm Trip) Processor 2 DIMM Thermal Trip C1h All (P2 Mem Thrm Trip) Processor 3 DIMM Thermal Trip C2h All (P3 Mem Thrm Trip) Processor 4 DIMM Thermal Trip C3h All (P4 Mem Thrm Trip) Global Aggregate Temperature Margin 1 Appendix B: Integrated BMC Sensor Tables Sensor Type Memory 0Ch Memory 0Ch Memory 0Ch Memory 0Ch Event/Reading Event Offset
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Global Aggregate Temperature Margin 3 Sensor # Platform Applicability Intel® Server Board S1400FP TPS Sensor Type Event/Reading Event Offset Triggers Type CAh Platform Specific Temperature Threshold 01h 01h CBh Platform Specific Temperature Threshold 01h 01h CCh Platform Specific Temperature Threshold 01h 01h CDh Platform Specific Temperature Threshold 01h 01h CEh Platform Specific Temperature Thre
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) Global Aggregate Temperature Margin 8 Sensor # CFh Platform Applicability Platform Specific Appendix B: Integrated BMC Sensor Tables Sensor Type Event/Reading Event Offset Triggers Type Temperature Threshold 01h 01h - Contrib.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard +1.05V Processor2 Vccp Sensor # D7h Platform Applicability All (BB +1.05Vccp P2) Baseboard +1.
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Intel® Server Board S1400FP TPS Full Sensor Name (Sensor name in SDR) Baseboard +1.1V Stand-by (BB +1.1V STBY) Baseboard CMOS Battery Sensor # DDh DEh Platform Applicability E4h Sensor Type Event/Reading Event Offset Triggers Type All Voltage 02h Threshold 01h All Voltage 02h Threshold 01h All Voltage 02h Threshold 01h (BB +3.3V Vbat) Baseboard +1.35V P1 Low Voltage Memory AB VDDQ Appendix B: Integrated BMC Sensor Tables [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] (BB +1.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard +3.3V Riser 1 Power Good Sensor # (HDD 1 - 15 Status) Event/Reading Event Offset Triggers Type EAh Voltage 02h Threshold 01h EBh Platform Specific Voltage 02h Threshold 01h (BB +3.3 RSR2 PGD) Hard Disk Drive 1 -15 Status Sensor Type Platform Specific (BB +3.3 RSR1 PGD) Baseboard +3.
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Intel® Server Board S1400FP TPS Appendix C: POST Code Diagnostic LED Decoder Appendix C: POST Code Diagnostic LED Decoder As an aid to assist in trouble shooting a system hang that occurs during a system’s Power-On Self Test (POST) process, the server board includes a bank of eight POST Code Diagnostic LEDs on the back edge of the server board.
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Appendix C: POST Code Diagnostic LED Decoder Intel® Server Board S1400FP TPS Table 62. POST Progress Code LED Example Upper Nibble AMBER LEDs LEDs Status Results MSB LED #7 8h ON 1 LED #6 4h OFF 0 LED #5 2h ON 1 Lower Nibble GREEN LEDs LED #4 1h OFF 0 LED #3 8h ON 1 Ah LED #2 4h ON 1 LED #1 2h OFF 0 LSB LED #0 1h OFF 0 Ch Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh The following table provides a list of all POST progress codes. Table 63.
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Intel® Server Board S1400FP TPS Appendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder 1 = LED On, 0 = LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED # #7 #6 #5 #4 #3 #2 #1 #0 78h 0 1 1 1 1 0 0 0 79h 0 1 1 1 1 0 0 1 90h 1 0 0 1 0 0 0 0 91h 1 0 0 1 0 0 0 1 92h 1 0 0 1 0 0 1 0 93h 1 0 0 1 0 0 1 1 94h 1 0 0 1 0 1 0 0 95h 1 0 0 1 0 1 0 1 96h 1 0 0 1 0 1 1 0 97h 1 0 0 1 0 1 1 1 98h 1 0 0 1 1 0 0 0 99h 1 0 0 1 1 0 0 1 9Ah 1 0 0 1 1 0 1 0 9Bh 1 0 0 1 1 0 1 1 9Ch 1 0
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Appendix C: POST Code Diagnostic LED Decoder Intel® Server Board S1400FP TPS POST Memory Initialization MRC Diagnostic Codes There are two types of POST Diagnostic Codes displayed by the MRC during memory initialization; Progress Codes and Fatal Error Codes. The MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in the MRC operational path at each step. Table 64.
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Intel® Server Board S1400FP TPS Appendix C: POST Code Diagnostic LED Decoder Table 65. POST Progress LED Codes Diagnostic LED Decoder 1 = LED On, 0 = LED Off Checkpoint Upper Nibble Lower Nibble Description MSB LED LSB 8h 4h 2h 1h 8h 4h 2h 1h #7 #6 #5 #4 #3 #2 #1 #0 MRC Fatal Error Codes E8h E9h 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 EAh EBh EDh EFh Revision 2.
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Appendix D: POST Code Errors Intel® Server Board S1400FP TPS Appendix D: POST Code Errors Most error conditions encountered during POST are reported using POST Error Codes. These codes represent specific failures, warnings, or are informational. POST Error Codes may be displayed in the Error Manager display screen, and are always logged to the System Event Log (SEL). Logged events are available to System Management applications, including Remote and Out of Band (OOB) management.
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Intel® Server Board S1400FP TPS Appendix D: POST Code Errors Table 66. POST Error Codes and Messages Error Code 0012 0048 0140 0141 0146 0191 0192 0194 0195 0196 0197 5220 5221 5224 8130 8131 8132 8133 8160 8161 8162 8163 8170 8171 8172 8173 8180 8181 8182 8183 8190 8198 8300 8305 83A0 83A1 84F2 84F3 84F4 84FF 8500 8501 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 852A 852B 852C Revision 2.
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Appendix D: POST Code Errors Error Code 852D 852E 852F 8530 8531 8532 8533 8534 8535 8536 8537 8538 8539 853A 853B 853C 853D 853E 853F (Go to 85C0) 8540 8541 8542 8543 8544 8545 8546 8547 8548 8549 854A 854B 854C 854D 854E 854F 8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 855A 855B 855C 855D 855E 855F (Go to 85D0) 8560 8561 8562 142 Intel® Server Board S1400FP TPS DIMM_E2 failed test/initialization DIMM_E3 failed test/initialization DIMM_F1 failed test/initialization DIMM_F2 failed test/initializati
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Intel® Server Board S1400FP TPS Error Code 8563 8564 8565 8566 8567 8568 8569 856A 856B 856C 856D 856E 856F 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 857A 857B 857C 857D 857E 857F (Go to 85E0) 85C0 85C1 85C2 85C3 85C4 85C5 85C6 85C7 85C8 85C9 85CA 85CB 85CC 85CD 85CE 85CF 85D0 85D1 85D2 85D3 85D4 85D5 85D6 85D7 85D8 85D9 85DA Revision 2.
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Appendix D: POST Code Errors Error Code 85DB 85DC 85DD 85DE 85DF 85E0 85E1 85E2 85E3 85E4 85E5 85E6 85E7 85E8 85E9 85EA 85EB 85EC 85ED 85EE 85EF 8604 8605 8606 92A3 92A9 A000 A001 A002 A003 A100 A421 A5A0 A5A1 A6A0 Intel® Server Board S1400FP TPS Error Message DIMM_O2 disabled DIMM_O3 disabled DIMM_P1 disabled DIMM_P2 disabled DIMM_P3 disabled DIMM_K3 encountered a Serial Presence Detection (SPD) failure DIMM_L1 encountered a Serial Presence Detection (SPD) failure DIMM_L2 encountered a Serial Presence De
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Intel® Server Board S1400FP TPS Beeps 4 Error Message BIOS Recovery failure Appendix D: POST Code Errors POST Progress Code NA Description BIOS recovery has failed. This typically happens so quickly after recovery us initiated that it sounds like a 2-4 beep code. The Integrated BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded each time the problem is discovered, such as on each power-up attempt, but are not sounded continuously.
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Appendix E: Supported Intel® Server Chassis Intel® Server Board S1400FP TPS Appendix E: Supported Intel® Server Chassis The Intel® Server Board S1400FP requires a passive processor heatsink solution when integrated in the Intel® pedestal server chassis listed below. The Intel® Server Board S1400FP supports up to 95W TDP Intel® Xeon® Processor. ® Table 69.
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Intel® Server Board S1400FP TPS Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) with alpha entries following (for example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
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Glossary Intel® Server Board S1400FP TPS Term 2 Definition IC Inter-integrated Circuit bus IA Intel Architecture IBF Input buffer ICH I/O Controller Hub IERR Internal error INIT Initialization signal IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface ITP In-target probe KCS Keyboard controller style KT Keyboard text KVM Keyboard, video, mouse LAN Local area network LCD Liquid crystal display LPC Low pin count LUN Logical unit number MA
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Intel® Server Board S1400FP TPS Glossary Term ROM Read-Only Memory RTC Real-Time Clock SCI System Control Interrupt. A system interrupt used by hardware to notify the operating system of ACPI events. SDR Sensor Data Record SDRAM Synchronous Dynamic Random Access Memory SEL System Event Log SHA1 Secure Hash Algorithm 1 SIO Server Input/Output SMBus* A two-wire interface based on the I C protocol.
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Reference Documents Intel® Server Board S1400FP TPS Reference Documents See the following documents for additional information: 150  Advanced Configuration and Power Interface Specification, Revision 3.0, http://www.acpi.info/.  Intelligent Platform Management Bus Communications Protocol Specification, Version 1.0, 1998. Intel Corporation, Hewlett-Packard* Company, NEC* Corporation, Dell* Computer Corporation.  Intelligent Platform Management Interface Specification, Version 2.0, 2004.