Intel®Server Board S1200V3RP Technical Product Specification Intel reference number G84364-004 Revision 1.
Revision History Intel®Server Board S1200V3RP TPS Revision History Date November 2012 Revision Number 0.5 May 2013 1.0 Updated BIOS Setup Interface Changed the chipset of S1200V3RPL to C226 October 2013 1.1 Updated Graphics Controller and Video output: Changed the supporting OS for pGFX Display Port video output to Microsoft Windows 7*. January 2014 1.2 Added Backup BIOS update instruction. July 2014 1.3 Updated TPM module information. ii Modifications Preliminary release. Revision 1.
Intel®Server Board S1200V3RP TPS Disclaimers Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Table of Contents Intel®Server Board S1200V3RP TPS Table of Contents 1. Introduction ........................................................................................................................ 1 1.1 Chapter Outline ...................................................................................................... 1 1.2 Server Board Use Disclaimer ................................................................................. 2 2. Overview .................................................
Intel®Server Board S1200V3RP TPS Table of Contents 4. System Security................................................................................................................ 33 4.1 BIOS Password Protection ................................................................................... 33 4.2 Trusted Platform Module (TPM) Support .............................................................. 34 4.2.1 TPM security BIOS .............................................................................
Table of Contents Intel®Server Board S1200V3RP TPS 6.11.12 SM-CLP (SM-CLP Lite) ........................................................................................ 62 6.11.13 Embedded Web Server ........................................................................................ 63 6.11.14 Virtual Front Panel ............................................................................................... 64 6.11.15 Embedded Platform Debug ...........................................................
Intel®Server Board S1200V3RP TPS Table of Contents 8.5.3 SATA Connectors ................................................................................................ 83 8.5.4 Serial Port Connectors ......................................................................................... 83 8.5.5 USB Connector .................................................................................................... 84 8.5.6 I/O Module Connector ................................................................
Table of Contents Intel®Server Board S1200V3RP TPS 13.1.5 Dynamic Loading ............................................................................................... 215 13.1.6 Capacitive Loading ............................................................................................. 215 13.1.7 Grounding .......................................................................................................... 215 13.1.8 Residual Voltage Immunity in Standy mode ....................................
Intel®Server Board S1200V3RP TPS List of Figures List of Figures Figure 1. Intel® Server Board S1200V3RP Layout....................................................................... 5 Figure 2. Intel® Server Board S1200V3RPL and S1200V3RPS Layout ....................................... 6 Figure 3. Intel® Server Board S1200V3RPO and S1200V3RPM Layout ...................................... 7 Figure 4. Intel® Server Board S1200V3RP – Mounting Hole Locations .......................................
List of Figures Intel®Server Board S1200V3RP TPS Figure 40. Network Device Order Screen ................................................................................ 185 Figure 41. BEV Device Order Screen...................................................................................... 186 Figure 42. Add EFI Boot Option Screen .................................................................................. 187 Figure 43. Delete EFI Boot Option Screen ..............................................
Intel®Server Board S1200V3RP TPS List of Tables List of Tables Table 1. Intel® Server Board S1200V3RP Feature Set ................................................................ 3 Table 2. UDIMM Support Guidelines ......................................................................................... 15 Table 3. Intel® Server Board S1200V3RP DIMM Nomenclature ................................................ 16 Table 4. Intel® Server Board S1200V3RP DIMM Maximum Configuration ...........................
List of Tables Intel®Server Board S1200V3RP TPS Table 40. Power/Sleep LED Functional States .......................................................................... 81 Table 41. NMI Signal Generation and Event Logging ................................................................ 81 Table 42. VGA Connector Pin-out (J7A1).................................................................................. 82 Table 43. Display Port Connector Pin-out (J8A1) ..................................................
Intel®Server Board S1200V3RP TPS List of Tables < This page intentionally left blank. > Revision 1.
Intel®Server Board S1200V3RP TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of the Intel® Server Board series S1200V3RP family. Design-level information related to specific server board components and subsystems can be obtained by ordering External Product Specifications (EPS) or External Design Specifications (EDS) related to this server generation.
Introduction 1.2 Intel®Server Board S1200V3RP TPS Server Board Use Disclaimer Intel Corporation server boards support add-in peripherals and contain a number of high-density Very Large Scale Integration (VLSI) and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components.
Intel®Server Board S1200V3RP TPS 2. Overview Overview The Intel® Server Board S1200V3RPL, S1200V3RPS, S1200V3RPO, and S1200V3RPM are monolithic printed circuit boards (PCBs) with features designed to support the pedestal or rack server markets. These server boards are designed to support the Intel® Xeon® processor E3 1200 V3 product family. Previous generation Intel® Xeon® processors are not supported. Many of the features and functions of these four server boards are common.
Overview Intel®Server Board S1200V3RP TPS Feature Description 3Gbps through six onboard SATA connectors. RAID Support Intel® RSTe SW RAID through onboard SATA connectors provides SATA RAID 0/1/10/5. Intel® Embedded Server RAID Technology II through onboard SATA connectors provides SATA RAID 0/1/10 and optional RAID 5 support provided by the Intel ® RAID Activation Key RKSATA4R5.
Intel®Server Board S1200V3RP TPS 2.2 Overview Server Board Layout Figure 1. Intel®Server Board S1200V3RP Layout 2.2.1 Server Board Connector and Component Layout The following figure shows the layout of the server board. Each connector and major component is identified by a number or letter, and a description is given in the figure below. Revision 1.
Overview Intel®Server Board S1200V3RP TPS Figure 2. Intel®Server Board S1200V3RPL and S1200V3RPS Layout 6 Revision 1.
Intel®Server Board S1200V3RP TPS Overview Figure 3. Intel®Server Board S1200V3RPO and S1200V3RPM Layout Revision 1.
Overview 2.2.2 Intel®Server Board S1200V3RP TPS Server Board Mechanical Drawings Figure 4. Intel®Server Board S1200V3RP – Mounting Hole Locations 8 Revision 1.
Intel®Server Board S1200V3RP TPS Overview Figure 5. Intel®Server Board S1200V3RP – Major Connector Pin-1 Locations Revision 1.
Overview Intel®Server Board S1200V3RP TPS Figure 6. Intel®Server Board S1200V3RP – Primary Side Keepout Zone 10 Revision 1.
Intel®Server Board S1200V3RP TPS Overview Figure 7. Intel®Server Board S1200V3RP – Second Side Keepout Zone 2.2.3 Server Board Rear I/O Layout The following drawing shows the layout of the rear I/O components for the server board. Figure 8. Intel®Server Board S1200V3RP Rear I/O Layout Revision 1.
Functional Architecture 3. Intel®Server Board S1200V3RP TPS Functional Architecture The architecture and design of the Intel® Server Board S1200V3RP is based on the Intel® C220 series chipset. The chipset is designed for systems based on the Intel® Xeon® processor in an LGA 1150 Socket H3 package. The Intel® Server Board S1200V3RPO uses Intel® C224 chipset. The Intel® Server Board S1200V3RPS uses Intel® C222 chipset. The Intel® Server Board S1200V3RPL and S1200V3RPM use Intel® C226 chipset.
Intel®Server Board S1200V3RP TPS Functional Architecture Note: The previous generation Intel® Xeon® processors are not supported on the Intel® server board described in this document. 3.1.
Functional Architecture Intel®Server Board S1200V3RP TPS Intel® 64 Architecture Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) Intel® Advanced Vector Extensions 2.
Intel®Server Board S1200V3RP TPS Functional Architecture The memory slots are named as Slot1 and Slot2 on each channel. Slot1 is the farthest from the processor socket. DIMMs are named to reflect the channel and slot in which they are installed: Channel A, Slot1 is DIMM_A1. Channel A, Slot2 is DIMM_A2. Channel B, Slot1 is DIMM_B1. Channel B, Slot2 is DIMM_B2. - 3.3.1 Supported Memory Single Ranked x8 unbuffered ECC Dual Ranked x8 unbuffered ECC Table 2.
Functional Architecture Intel®Server Board S1200V3RP TPS When only one memory channel is populated, the memory runs in Single Channel mode, with no interleaving. On the Intel® Server Board S1200V3RP, a total of 4 DIMM slots is provided. The nomenclature for DIMM sockets is detailed in the following table. - Table 3. Intel®Server Board S1200V3RP DIMM Nomenclature (0) Channel A A1 (1) Channel B A2 B1 B2 Figure 10. Intel®Server Board S1200V3RP DIMM Slot Layout Table 4.
Intel®Server Board S1200V3RP TPS 3.3.1.2 Functional Architecture Publishing System Memory The BIOS displays the Total Memory of the system during POST if Display Logo is disabled in the BIOS setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system. The BIOS displays the Effective Memory of the system in the BIOS setup.
Functional Architecture Intel®Server Board S1200V3RP TPS product family board is set at 10 events. When the 10th CE occurs, a single Correctable Error event is logged. 3.3.3 Post Error Codes The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late POST, this same range of POST code values is used for reporting other system errors.
Intel®Server Board S1200V3RP TPS Functional Architecture - Gen3 speeds at 8 GT/s (no 8b/10b encoding) - Can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s The Intel® Server Board S1200V3RPL and S1200V3RPS support PCIe slots: Slot 7: PCI Express* Gen2 x1 electrical with x8 physical connector, from PCH. Slot 6: PCI Express* Gen2 x 16 or Gen3 x8 electrical with x16 physical connector, from processor. - Slot 5: PCI Express* Gen2 x8 or x4 electrical with x8 physical connector, from processor.
Functional Architecture Intel®Server Board S1200V3RP TPS Direct Media Interface (DMI) Direct Media Interface (DMI) connects the processor and the PCH. DMI2.0 is supported. Note: Only DMI x4 configuration is supported. - 3.3.5 DMI 2.0 support. Compliant to Direct Media Interface Second Generation (DMI2). Four lanes in each direction. 5 GT/s point-to-point DMI interface to PCH is supported.
Intel®Server Board S1200V3RP TPS Functional Architecture attaches to a high density 80-pin connector on the server board (J1C1) labeled I/O_MOD and is supported by up to x8 PCIe Gen3 signals from the IIO module of the processor. 3.3.7 Intel®I/O Acceleration Technolgy 2 (Intel®I/O AT2) Intel® I/O AT2 is not supported. 3.3.7.1 Direct Cache Access (DCA) Direct Cache Access (DCA) is not supported on Intel® Xeon® Processor E3-1200 v3 series. 3.
Functional Architecture Intel®Server Board S1200V3RP TPS Gigabit Ethernet Controller RTC GPIO Enhanced Power Management Manageability System Management Bus (SMBus* 2.0) Integrated NVSRAM controller Virtualization Technology for Direct I/O (Intel® VT-d) JTAG Boundary-Scan KVM/Serial Over LAN (SOL) Function 3.4.1 Digital Media Interface (DMI) Digital Media Interface (DMI) is the chip-to-chip connection between the processor and the Intel® C220 series chipset.
Intel®Server Board S1200V3RP TPS 3.4.3.1 Functional Architecture AHCI The Intel® C220 series chipset provides hardware support for Advanced Host Controller Interface (AHCI), a standardized programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug.
Functional Architecture Intel®Server Board S1200V3RP TPS Board Management Controller as well as providing support for the optional Trusted Platform Module (TPM). 3.4.5 Serial Peripheral Interface (SPI) ® The Intel C220 series chipset implements an SPI Interface as an alternative interface for the BIOS flash device. 3.4.6 Universal Serial Bus (USB) Controller ® The Intel C220 series chipset has up to two Enhanced Host Controller Interface (EHCI) host controllers that support USB high-speed signaling.
Intel®Server Board S1200V3RP TPS 3.4.6.2 Functional Architecture Legacy USB Support The BIOS supports PS/2 emulation of USB keyboards and mouse. During POST, the BIOS initializes and configures the root hub ports and searches for a keyboard and/or a mouse on the USB hub and then enables the devices that are recognized. 3.4.6.3 eUSB SSD Support The server board provides support for a low profile eUSB SSD storage device.
Functional Architecture Intel®Server Board S1200V3RP TPS LED Color Green (Left) 3.4.7.
Intel®Server Board S1200V3RP TPS Functional Architecture machine through the network without the need to be physically near that machine. Text, mouse, and keyboard redirection allows the remote machine to control and configure the client by entering BIOS setup. The KVM/SOL function emulates a standard PCI serial port and redirects the data from the serial port to the management console using LAN. KVM has additional requirements of internal graphics and SOL may be used when KVM is not supported. 3.4.
Functional Architecture Intel®Server Board S1200V3RP TPS Figure 12. Integrated Baseboard Management Controller (BMC) Overview Figure 13. Integrated BMC Functional Block Diagram 28 Revision 1.
Intel®Server Board S1200V3RP TPS 3.5.
Functional Architecture Intel®Server Board S1200V3RP TPS The BIOS supports dual-video mode when an add-in video card is installed. In the single mode (dual monitor video = disabled), the on-board video controller is disabled when an add-in video card is detected. In the dual mode (on-board video = enabled, dual monitor video = enabled), the onboard video controller is enabled and is the primary video device. The add-in video card is allocated resources and is considered the secondary video device.
Intel®Server Board S1200V3RP TPS 3.5.3 Functional Architecture Baseboard Management Controller The server board utilizes the following features of the embedded baseboard management controller: IPMI 2.
Functional Architecture 3.5.3.2 Intel®Server Board S1200V3RP TPS Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10/100 network interfaces. These interfaces are not shared with the host system. At any time, only one dedicated interface may be enabled for management traffic. The default active interface is the NIC 1 port. For these channels, support can be enabled for IPMI-over-LAN and DHCP.
Intel®Server Board S1200V3RP TPS System Security 4. System Security 4.1 BIOS Password Protection The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords can restrict entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress automatic USB device reordering. There is also an option to require a Power On password entry in order to boot the system.
System Security Intel®Server Board S1200V3RP TPS prompts for a password, and can only be used with the Administrator password. Also, when a User password is defined, it suppresses the USB Reordering that occurs, if enabled, when a new USB boot device is attached to the system. A User is restricted from booting in anything other than the Boot Order defined in the Setup by an Administrator.
Intel®Server Board S1200V3RP TPS System Security Provides BIOS Setup options to change TPM security states and to clear TPM ownership. For additional details, refer to the TCG PC Client Specific Implementation Specification, the TCG PC Client Specific Physical Presence Interface Specification, and the Microsoft BitLocker* Requirement documents. 4.2.
System Security Intel®Server Board S1200V3RP TPS When the Setup is entered, the Main screen displays. The BIOS Setup utility provides the Security screen to enable and set the user and administrative passwords and to lock out the front panel buttons so they cannot be used. The Intel® Server Board S1200V3RP provides TPM settings through the security screen. To access this screen from the Main screen, select the Security option. Figure 14. Setup Utility – TPM Configuration Screen Table 12.
Intel®Server Board S1200V3RP TPS Setup Item Options System Security Help Text Comments is in the same state as a disabled TPM except setting of TPM ownership is allowed if not present already. An enabled and activated TPM executes all commands that use TPM functions and TPM security operations will be available. TPM Administrative Control** 4.3 No Operation Turn On Turn Off Clear Ownership [No Operation] - No changes to current state. [Turn On] - Enables and activates TPM.
Intel®Technology Support 5. Intel®Technology Support 5.1 Intel®Trusted Execution Technology Intel®Server Board S1200V3RP TPS The Intel® Xeon® Processor E3-1200 v3 Product Families support Intel® Trusted Execution Technology (Intel® TXT), which is a robust security environment designed to help protect against software-based attacks. Intel® Trusted Execution Technology integrates new security features and capabilities into the processor, chipset, and other platform components.
Intel®Server Board S1200V3RP TPS Intel®Technology Support For more information on the DMAR table and the DRHD entry format, refer to the Intel® Virtualization Technology for Directed I/O Architecture Specification. For more general information about VT-x, VT-d, and VT-c, a good reference is Enabling Intel® Virtualization Technology Features and Benefits White Paper. 5.
Intel®Technology Support Intel®Server Board S1200V3RP TPS changes for power limiting. PMBus*-compliant power supplies provide the capability to monitoring input power consumption, which is necessary to support NM. Following are the some of the applications of Intel® Intelligent Power Node Manager technology: Platform Power Monitoring and Limiting: The ME/NM monitors platform power consumption and holds average power over duration.
Intel®Server Board S1200V3RP TPS Intel®Technology Support Value Vector Power and Thermal Policies Avoid Triggering HW Protection Interfaces 5.3.1 Capabilities and Features Concurrent policies 2.
Platform Management Functional Overview 6. Intel®Server Board S1200V3RP TPS Platform Management Functional Overview Platform management functionality is supported by several hardware and software components integrated on the server board that work together to control system functions, monitor and report system health, and control various thermal and performance features in order to maintain (when possible) server functionality in the event of component failure and/or environmentally stressed conditions.
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview See also the Intelligent Platform Management Interface Specification Second Generation v2.0. 6.1.2 Non-IPMI Features The BMC supports the following non-IPMI features.
Platform Management Functional Overview Intel®Server Board S1200V3RP TPS Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported on embedded NICs). Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on embedded NICs).
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview Feature Diagnostic Beep Code Support Yes Basic* Advanced** Yes Power State Retention Yes Yes ARP/DHCP Support Yes Yes PECI Thermal Management Support Yes Yes E-mail Alerting Yes Yes Embedded Web Server Yes Yes SSH Support Yes Yes Integrated KVM Yes Integrated Remote Media Redirection Yes Lightweight Directory Access Protocol (LDAP) Yes Yes Intel® Intelligent Power Node Manager Support*** Yes Yes SMASH
Platform Management Functional Overview 6.4 Intel®Server Board S1200V3RP TPS Power Control Sources The server board supports several power control sources which can initiate a power-up or power-down activity. Table 17.
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview 2. Reversion of temporary test modes for the BMC back to normal operational modes. 3. FP status LED and DIMM fault LEDs may not reflect BIOS detected errors. 6.6 Fault Resilient Booting (FRB) Fault resilient booting (FRB) is a set of BIOS and BMC algorithms and hardware support that allow a multiprocessor system to boot even if the bootstrap processor (BSP) fails. Only FRB2 is supported using watchdog timer commands.
Platform Management Functional Overview Intel®Server Board S1200V3RP TPS See Appendix B – Integrated BMC Sensor Tables for additional sensor information. 6.8 Field Replaceable Unit (FRU) Inventory Device The BMC implements the interface for logical FRU inventory devices as specified in the Intelligent Platform Management Interface Specification, Version 2.0. This functionality provides commands used for accessing and managing the FRU inventory information.
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview might require a trade-off between fan speed and system performance parameters that contribute to the cooling requirements, primarily memory bandwidth. The BIOS, BMC, and SDRs work together to provide control over how this trade-off is determined. This capability requires the BMC to access temperature sensors on the individual memory DIMMs.
Platform Management Functional Overview 2. 3. 4. 5. 6. 7. 8. 9. Intel®Server Board S1200V3RP TPS For fan speed control in 3rd party chassis Temperature margin from throttling threshold Absolute temperature PECI value or margin value On-die sensor On-board sensor Virtual sensor Available only when PSU has PMBus* The following illustration provides a simple model showing the fan speed control structure that implements the resulting fan speeds. Figure 15. Fan Speed Control Process 6.10.
Intel®Server Board S1200V3RP TPS Type Platform Management Functional Overview Profile Details OLTT 7 Performance, 3000M altitude CLTT 0 300M altitude CLTT 2 900M altitude CLTT 4 1500M altitude CLTT 6 3000M altitude Each group of profiles allows for varying fan control policies based on the altitude.
Platform Management Functional Overview Intel®Server Board S1200V3RP TPS Both Static and Dynamic CLTT modes implement a Hybrid Closed Loop Thermal Throttling mechanism whereby the Integrated Memory Controller estimates the DRAM temperature in between actual reads of the memory thermal sensors. 6.
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview 2. User 2 (“root”) always has the administrator privilege level. 3. All user passwords (including passwords for 1 and 2) may be modified. User IDs 3-15 may be used freely, with the condition that user names are unique. Therefore, no other users can be named “” (Null), “root,” or any other existing user name. 6.11.
Platform Management Functional Overview Intel®Server Board S1200V3RP TPS The baseboard NICs are connected to a single BMC RMII/RGMII port that is configured for RMII operation. The NC-SI protocol is used for this connection and provides a 100 Mb/s full-duplex multi-drop interface which allows multiple NICs to be connected to the BMC. The physical layer is based upon RMII, however RMII is a point-to-point bus whereas NC-SI allows 1 master and up to 4 slaves.
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview The printed MAC address on the server board and/or server system is assigned to NIC1 on the server board. For security reasons, embedded LAN channels have the following default settings: IP Address: Static All users disabled IPMI-enabled network interfaces may not be placed on the same subnet. This includes the Intel® Dedicated Server Management NIC and either of the BMC’s embedded network interfaces.
Platform Management Functional Overview Intel®Server Board S1200V3RP TPS configured by Router Advertisements from the local router. The IP, Prefix, and Gateway are read-only parameters to the BMC user in this mode. Stateless auto-config: The Prefix and Gateway are configured by the router through Router Advertisements. The BMC derives its IP in two parts: the upper network portion comes from the router and the lower unique portion comes from the BMC’s channel MAC address.
Intel®Server Board S1200V3RP TPS 6.11.3.5.1 Platform Management Functional Overview Static IP Address (IP Address Source Values 0h, 1h, and 3h) The BMC supports static IP address assignment on all of its management NICs. The IP address source parameter must be set to static before the IP address; the subnet mask or gateway address can be manually set.
Platform Management Functional Overview Intel®Server Board S1200V3RP TPS running DHCP”. Once this parameter is set, the BMC initiates the DHCP process within approximately 100 ms. If the BMC has previously been assigned an IP address through DHCP or the Set LAN Configuration Parameter command, it requests that same IP address to be reassigned. If the BMC does not receive the same IP address, system management software must be reconfigured to use the new IP address.
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview User should always set the hostname starting from block selector 1 after the last Update is complete. If the user skips block selector 1 while setting the hostname, the BMC will record the hostname as NULL, because the first block contains NULL data. This scheme effectively does not allow a user to make a partial Hostname change. Any Hostname change needs to start from Block 1.
Platform Management Functional Overview Intel®Server Board S1200V3RP TPS Parameter 25 (VLAN Destination Address) of the Set LAN Config Parameters IPMI command is not supported and returns a completion code of 0x80 (parameter not supported) for any read/write of parameter 25.
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview Table 20.
Platform Management Functional Overview 6.11.11 Intel®Server Board S1200V3RP TPS Alert Policy Table Associated with each PEF entry is an alert policy that determines which IPMI channel the alert is to be sent. There is a maximum of 20 alert policy entries. There are no pre-configured entries in the alert policy table because the destination types and alerts may vary by user. Each entry in the alert policy table contains four bytes for a maximum table size of 80 bytes. 6.11.11.
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview The embedded web server is supported over any system NIC port that is enabled for server management capabilities. 6.11.13 Embedded Web Server BMC Base manageability provides an embedded web server and an OEM-customizable web GUI which exposes the manageability features of the BMC base feature set.
Platform Management Functional Overview Online help. Display/clear SEL (display is in easily understandable human readable format). Support major industry-standard browsers (Microsoft Internet Explorer* and Mozilla Firefox*). Automatically log out after user-configurable inactivity period. The GUI session automatically times-out after a user-configurable inactivity period. By default, this inactivity period is 30 minutes.
Intel®Server Board S1200V3RP TPS Platform Management Functional Overview For Reset from Virtual Front Panel, the restart cause will be because of Chassis Control command. During Power action, Power button/Reset button will not accept the next action until current Power action is complete and the acknowledgment from BMC is received. EWS will provide a valid message during Power action until it completes the current Power action.
Platform Management Functional Overview Intel®Server Board S1200V3RP TPS BMC configuration data BMC FW debug log (that is, SysLog) – Captures FW debug messages. Non-volatile storage of captured data – Some of the captured data is stored persistently in the BMC’s non-volatile flash memory and preserved across AC power cycles. Due to size limitations of the BMC’s flash memory, it is not feasible to store all of the data persistently.
Intel®Server Board S1200V3RP TPS 6.11.15.3 Platform Management Functional Overview Output Data Categories The following tables list the data to be provided in the diagnostic output. Table 21.
Platform Management Functional Overview 6.11.17 Intel®Server Board S1200V3RP TPS Lightweight Directory Authentication Protocol (LDAP) The Lightweight Directory Access Protocol (LDAP) is an application protocol supported by the BMC for the purpose of authentication and authorization. The BMC user connects with an LDAP server for login authentication. This is only supported for non-IPMI logins including the embedded web UI and SM-CLP. IPMI users/passwords and sessions are not supported over LDAP.
Intel®Server Board S1200V3RP TPS 7. Advanced Management Feature Support (RMM4) Advanced Management Feature Support (RMM4) The integrated baseboard management controller has support for advanced management features which are enabled when an optional Intel® Remote Management Module 4 (RMM4) is installed. RMM4 is comprised of two boards: RMM4 lite and the optional Dedicated Server Management NIC (DMN). Table 23.
Advanced Management Feature Support (RMM4) Intel®Server Board S1200V3RP TPS Figure 17. Intel®RMM4 Dedicated Management NIC Installation Table 24. Enabling Advanced Management Features Manageability Hardware ® Benefits Intel Integrated BMC Comprehensive IPMI based base manageability features Intel® Remote Management Module 4 – Lite Package contains one module – Key for advance Manageability features.
Intel®Server Board S1200V3RP TPS Advanced Management Feature Support (RMM4) keyboard redirection are supported. It is also possible to use the KVM-redirection (KVM-r) session concurrently with media-redirection (media-r). This feature allows a user to interactively use the keyboard, video, and mouse functions of the remote server as if the user were physically at the managed server.
Advanced Management Feature Support (RMM4) Intel®Server Board S1200V3RP TPS the firewall and, in case of a private internal network, the NAT (Network Address Translation) settings have to be configured accordingly. 7.1.2 Performance The remote display accurately represents the local display. The feature adapts to changes to the video resolution of the local display and continues to work smoothly when the system transitions from graphics to text or vice versa.
Intel®Server Board S1200V3RP TPS Advanced Management Feature Support (RMM4) Once mounted, the remote device appears just like a local device to the server, allowing system administrators or users to install software (including operating systems), copy files, update BIOS, and so on, or boot the server from this device. The following capabilities are supported: The operation of remotely mounted devices is independent of the local devices on the server.
Advanced Management Feature Support (RMM4) 74 5124 – CD Redirection (Secure) 5127 – FD Redirection (Secure) 7578 – Video Redirection 7582 – Video Redirection (Secure) Intel®Server Board S1200V3RP TPS Revision 1.
Intel®Server Board S1200V3RP TPS 8. On-board Connector/Header Overview On-board Connector/Header Overview The following section provides detailed information regarding all connectors, headers, and jumpers on the server boards. 8.1 Board Connector Information The following table lists all connector types available on the board and the corresponding preference designators printed on the silkscreen. Table 25.
On-board Connector/Header Overview Connector Intel®Server Board S1200V3RP TPS Quantity Reference Designators Connector Type Pin Count SATA 6 J1K4, J1K1, J1K5, J1K2, J2K5, J2K3 Connector 7 HSBP_I2C 1 J2K4 Header 3 SATA SGPIO 1 J2K2 Header 5 LCP 1 J1G1 Header 7 IPMB 1 J2K1 Header 4 Configuration jumpers 5 J3K6 (Force Integrated BMC update), J2K9 (Password Clear), J2K8 (BIOS Recovery), J2K6 (Reset BIOS Configuration) J3K2 (ME Firmware Update) Jumper 3 TPM 1 J8J1 Connecto
Intel®Server Board S1200V3RP TPS On-board Connector/Header Overview Table 27. CPU Power Connector Pin-out (J9B1) Pin 1 Signal GND of Pin 5 Color Black 2 GND of Pin 6 Black 3 GND of Pin 7 Black 4 GND of Pin 8 Black 5 +12 Vdc CPU1 Yellow/black 6 +12 Vdc CPU1 Yellow/black 7 +12 Vdc DDR3_CPU1 Yellow/black 8 +12 Vdc DDR3_CPU1 Yellow/black Table 28. Power Supply Auxiliary Signal Connector Pin-out (J9C3) 8.
On-board Connector/Header Overview Intel®Server Board S1200V3RP TPS Pin 25 GND Signal Name Pin 26 TX_CLK Signal Name 27 GND 28 RX_CLK 29 GND 30 PRESENT# Table 30. Intel®RMM4 – Lite Connector Pin-out (J4B1) Pin 8.3.2 1 Signal Name 3V3_AUX 2 Pin Signal Name SPI_RMM4_LITE_DI 3 KEY PIN 4 SPI_RMM4_LITE_CLK 5 SPI_RMM4_LITE_DO 6 GND 7 SPI_RMM4_LITE_CS_N 8 GND TPM connector Table 31. TPM connector Pin-out (J8J1) 8.3.
Intel®Server Board S1200V3RP TPS 8.3.5 On-board Connector/Header Overview Pin 6 Signal Name FM_LCP_LEFT_N 7 FM_LCP_RIGHT_N HSBP_ I2C Header Table 34. HSBP_ I2C Header Pin-out (J2K4) Pin 8.3.6 1 Signal Name SMB_HSBP_3V3STBY_DATA 2 GND 3 SMB_HSBP_3V3STBY_CLK HDD LED Header The server board includes a 2-pin hard drive activity LED header used with some SAS/SATA controller add-in cards. The header has the following pin-out. Table 35. HDD LED Header Pin-out (J1G2) Pin 1 8.3.
On-board Connector/Header Overview 8.3.9 Intel®Server Board S1200V3RP TPS IPMB Connector Table 38. IPMB Connector Pin-out (J2K1) Pin 8.4 Signal Name 1 GND 2 P12V 3 FAN_PWM 4 FAN_TACH Front Panel Connector The server board provides a 24-pin front panel connector (J1E1) for use with Intel® and thirdparty chassis. The connector consists of a 24-pin SSI compatible front panel connector.
Intel®Server Board S1200V3RP TPS On-board Connector/Header Overview Table 40. Power/Sleep LED Functional States State Power Mode LED Description Power-off Non-ACPI Off System power is off, and the BIOS has not initialized the chipset. Power-on Non-ACPI On System power is on S5 ACPI Off Mechanical is off, and the operating system has not saved any context to the hard disk. S4 ACPI Off Mechanical is off. The operating system has saved context to the hard disk.
On-board Connector/Header Overview 8.4.5 Intel®Server Board S1200V3RP TPS NIC Activity LED Support The Front Control Panel includes an activity LED indicator for each on-board Network Interface Controller (NIC). When a network link is detected, the LED will turn on solid. The LED will blink once network activity occurs at a rate that is consistent with the amount of network activity that is occurring. 8.4.
Intel®Server Board S1200V3RP TPS 8.5.2 On-board Connector/Header Overview Display Port Connector The following table details the pin-out definition of the Display Port connector (J8A1). Table 43. Display Port Connector Pin-out (J8A1) Pin 8.5.
On-board Connector/Header Overview Intel®Server Board S1200V3RP TPS Table 45. External DB9 Serial A Port Pin-out (J9A1) 1 Pin Signal Name SPA_DCD Description DCD (carrier detect) 2 SPA_SIN_N RXD (receive data) 3 SPA_OUT_N TXD (Transmit data) 4 SPA_DTR DTR (Data terminal ready) 5 GND Ground 6 SPA_DSR DSR (data set ready) 7 SPA_RTS RTS (request to send) 8 SPA_CTS CTS (clear to send) 9 SPA_RI RI (Ring Indicate) Table 46. Internal 9-pin Serial B Header Pin-out (J9A2) 8.5.
Intel®Server Board S1200V3RP TPS On-board Connector/Header Overview Table 48. Internal USB3.
On-board Connector/Header Overview 8.5.6 Intel®Server Board S1200V3RP TPS I/O Module Connector The following table details the pin-out definition of the I/O Module connector (J1C1). Table 51.
Intel®Server Board S1200V3RP TPS 8.5.7 On-board Connector/Header Overview SAS Module Connector The following table details the pin-out definition of the SAS Module connector (J4J1). Table 52. I/O Module Connector Pin-out (J4J1) Pin Revision 1.
On-board Connector/Header Overview 8.5.8 Intel®Server Board S1200V3RP TPS NIC1 with USB2.0 connector Location: JA6A1 Figure 18. NIC1 with USB2.0 connector 8.5.9 NIC2 with USB3.0 connector Location: JA5A1 Figure 19. NIC2 with USB3.0 connector 88 Revision 1.
Intel®Server Board S1200V3RP TPS 8.6 On-board Connector/Header Overview Fan Headers The server board provides five SSI-compliant 4-pin fans (J7K1, J3K4, J8K1, J8K2 and J8B1) to use as CPU and I/O cooling fans. 3-pin fans are supported on all fan headers. The pin configuration for each of the 4-pin fan headers is identical and defined in the following tables.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS 9. BIOS Setup Interface 9.1 HotKeys Supported During POST Certain “HotKeys” are recognized during POST. A HotKey is a key or a key combination that is recognized as an unprompted command input, that is, the operator is not prompted to press the HotKey and typically the HotKey will be recognized even while other processing is in progress. The Intel® Server Board S1200V3RP Family BIOS recognizes a number of HotKeys during POST.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Mouse devices detected, if any attached Instructions showing HotKeys for going to Setup, going to popup Boot Menu, starting Network Boot 9.3 BIOS Boot Pop-up Menu The BIOS Boot Specification (BBS) provides a Boot Pop-up menu that can be invoked by pressing the key during POST. The BBS Pop-up menu displays all available boot devices. The boot order in the pop-up menu is not the same as the boot order in the BIOS setup.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Note: If an Administrative Password has not been set, anyone who boots the system to Setup has access to all selection and data entry fields in Setup and can change any of them. 9.4.1.1 Setup Page Layout The Setup page layout is sectioned into functional areas. Each occupies a specific area of the screen and has dedicated functionality. The following table lists and describes each functional area.
Intel®Server Board S1200V3RP TPS Functional Area 9.4.1.2 BIOS Setup Interface Description than 29 characters, it is also broken to a new line, dividing the text at the last space (blank) character before the 29th character. An unbroken string of more than 29 characters will be arbitrarily wrapped to a new line after the 29th character. Text that extends beyond the end of the 11th line will not be displayed.
BIOS Setup Interface Key Intel®Server Board S1200V3RP TPS Option Select Menu Description The down arrow is used to select the next value in a menu item’s option list, or a value field’s pick list. The selected item must then be activated by pressing the key. Select Field The left and right arrow keys are used to move between the major menu pages. The keys have no effect if a sub-menu or pick list is displayed. - Change Value The key is used to move between fields.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface In the Option Values entry, the text for default values is shown with an underline. These values do not appear underline on the BIOS Setup screen. The underlined text in this document is to serve as a reference to which value is the default value. The Help Text entry is the actual text which appears on the screen to accompany the item when the item is the one in focus (active on the screen).
BIOS Setup Interface Categories (Top Tabs) Security Screen (Tab) Intel®Server Board S1200V3RP TPS 2nd Level Screens 3rd Level Screens Server Management Screen (Tab) Console Redirection System Information BMC LAN Configuration Boot Options Screen (Tab) CDROM Order Hard Disk Order Floppy Order Network Device Order BEV Device Order Add EFI Boot Option Delete EFI Boot Option Boot Manager Screen (Tab) Error Manager Screen (Tab) Save & Exit Screen (Tab) 9.4.2.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Screen Field Descriptions: 1. Logged in as: Option Values: Help Text: Comments: Information only. Displays password level that setup is running in: Administrator or User. With no passwords set, Administrator is the default mode. Back to [Main Screen] — [Screen Map] 2. Platform ID Option Values: Help Text: < Platform ID> Comments: Information only.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Platform: Identifies that this is the correct platform BIOS 86B: Identifies this BIOS as being an Intel Server BIOS xx: Major Revision level of the BIOS yy: Release Revision level for this BIOS zzzz: Release Number for this BIOS Back to [Main Screen] — [Screen Map] 5. Backup BIOS Version Option Values: Help Text: Comments: Information only.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Comments: Information only. Displays the total physical memory installed in the system, in MB or GB. The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs. Back to [Main Screen] — [Screen Map] 8. Quiet Boot Option Values: Enabled Disabled Help Text: [Enabled] – Display the logo screen during POST. [Disabled] – Display the diagnostic screen during POST.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS The year must be between 2005 and 2099. Use [Enter] or [Tab] key to select the next field. Use [+] or [-] key to modify the selected field. Comments: This field will initially display the current system day of week and date. It may be edited to change the system date. When the System Date is reset by the “BIOS Defaults” jumper, BIOS Recovery Flash Update, or other method, the date will be the earliest date in the allowed range – Saturday 01/01/2005.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Figure 21. Advanced Screen Screen Field Descriptions: 1. Processor Configuration Option Values: Help Text: View/Configure processor information and settings. Comments: Selection only. Select this line and press the key to go to the Processor Configuration group of configuration settings. Back to [Advanced Screen] — [Screen Map] 2. Memory Configuration Option Values: Help Text: View/Configure memory information and settings.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Comments: Selection only. Select this line and press the key to go to the Mass Storage Controller Configuration group of configuration settings. Back to [Advanced Screen] — [Screen Map] 4. PCI Configuration Option Values: Help Text: View/Configure PCI information and settings. Comments: Selection only. Select this line and press the key to go to the PCI Configuration group of configuration settings.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Comments: Selection only. Select this line and press the key to go to the System Acoustic and Performance Configuration group of configuration settings. Back to [Advanced Screen] — [Screen Map] 8. Network Stack Option Values: Help Text: Network Stack Settings. Comments: Selection only. Select this line and press the key to go to the Network Stack group of configuration settings. Back to [Advanced Screen] — [Screen Map] 9.4.2.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Figure 22. Processor Configuration Screen Screen Field Descriptions: 1. Processor ID Option Values: Help Text: Comments: Information only. Displays the Processor Signature value (from the CPUID instruction) identifying the type of processor and the stepping. S1200V3RP series boards have a single Processor ID display. 104 Revision 1.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Back to [Advanced Screen] — [Screen Map] 2. Processor Frequency Option Values: Help Text: Comments: processor. Information only. Displays current operating frequency of the Back to [Advanced Screen] — [Screen Map] 3. Microcode Revision Option Values: Help Text: Comments: Information only. Displays Revision Level of the currently loaded processor microcode.
BIOS Setup Interface Help Text: Intel®Server Board S1200V3RP TPS Comments: Information only. Displays size in MB of the processor L3 Cache. Since L3 cache is shared between all cores in a processor package, this is shown as the total amount of L3 cache per processor package. Back to [Advanced Screen] — [Screen Map] 7. Processor Version Option Values: Help Text: Comments: Information only. Displays Brand ID string read from processor with CPUID instruction.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Help Text: Intel(R) Turbo Boost Technology allows the processor to automatically increase its frequency if it is running below power, temperature, and current specifications. Comments: This option is only visible if all processors installed in the system support Intel® Turbo Boost Technology. In order for this option to be available, Enhanced Intel® SpeedStep® Technology must be Enabled. Back to [Advanced Screen] — [Screen Map] 11.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Disabled Help Text: Enable/Disable Processor C6 (ACPI C3) report to OS Comments: This is normally Enabled but can be Disabled for improved performance on certain benchmarks and in certain situations. Back to [Advanced Screen] — [Screen Map] 14. Intel(R) Hyper-Threading Tech Option Values: Enabled Disabled Help Text: Intel (R) Hyper-Threading Technology allows multithreaded software applications to execute threads in parallel within each processor.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Comments: The numbers of cores that appear as selections depends on the number of cores available in the processors installed. Boards may have as many as 8 cores in each of 1, 2, or 4 processors. The same number of cores must be active in each processor package. This Setup screen should begin with the number of currently-active cores as the number displayed. See note below – this may be different from the number previously set by the user.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Back to [Advanced Screen] — [Screen Map] 18. Intel(R) VT for Directed I/O Option Values: Enabled Disabled Help Text: Enable/Disable Intel (R) Virtualization Technology for Directed I/O (Intel (R) VT-d). Report the I/O device assignment to VMM through DMAR ACPI Tables. Comments: This option is only visible if all processors installed in the system support Intel® VT-d.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface whenever Intel® VT-d is enabled. In that case, this option will be shown as "Enabled", and grayed out and not changeable. Back to [Advanced Screen] — [Screen Map] 21. Intel(R) TXT Option Values: Enabled Disabled Help Text: Enable/Disable Intel(R) Trusted Execution Technology. Takes effect after reboot. Comments: Intel® TXT only appears when both Intel® Virtualization Technology and Intel® VT for Directed IO are enabled.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS MLC Streamer is a speculative prefetch unit within the processor(s). Note: Modifying this setting may affect performance. Comments: MLC Streamer is normally Enabled, for best efficiency in L2 Cache and Memory Channel use but disabling it may improve performance for some processing loads and on certain benchmarks. Back to [Advanced Screen] — [Screen Map] 24.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Disabled Help Text: The next cache line will be prefetched into L1 instruction cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 Instruction Cache and Memory Channel use but disabling it may improve performance for some processing loads and on certain benchmarks.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS To access this screen from the Main screen, select Advanced > Memory Configuration. To move to another screen, press the key to return to the Advanced screen, then select the desired screen. Figure 23. Memory Configuration Screen Screen Field Descriptions: 1. Total Memory Option Values: Help Text: Comments: Information only.
Intel®Server Board S1200V3RP TPS Comments: OS in MB or GB. BIOS Setup Interface Information only. Displays the amount of memory available to the The Effective Memory is the Total Physical Memory minus the sum of all memory reserved for internal usage, RAS redundancy and SMRAM. Note: some server operating systems do not display the total physical memory installed. Back to [Memory Configuration Screen] — [Advanced Screen] — [Screen Map] 3.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS 10 5 All None Help Text: Threshold value for logging Correctable Errors (CE) – Threshold of 10 (default) logs 10th CE, "All" logs every CE and “None”’ means no CE logging. All and None are not valid with Rank Sparing. Comments: Specifies how many Correctable Errors must occur before triggering the logging of a SEL Correctable Error Event. Only the first threshold crossing is logged, unless “All” is selected.
Intel®Server Board S1200V3RP TPS · BIOS Setup Interface Failed/Disabled – The DIMM installed in this slot has failed during initialization and/or was disabled during initialization. For each DIMM that is in the Installed & Operational state, the DIMM Size in GB of that DIMM is displayed. This is the physical size of the DIMM, regardless of how it is counted in the Effective Memory size.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Figure 24. Mass Storage Controller Configuration Screen Screen Field Descriptions: 1.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface If the SATA Controller is Disabled, the SATA Ports will not operate, and any installed SATA devices will be unavailable. Compatibility provides PATA emulation on the SATA device, allowing the use of legacy IDE/PATA drivers. Enhanced provides Native SATA support using native SATA drivers included with the vast majority of current OSes.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Intel(R) Integrated RAID Module Intel(R) Integrated RAID Module RMS25PB040 Intel(R) Integrated RAID Module RMT3PB080 Intel(R) Integrated RAID Module RMS25CB080 Intel(R) Integrated RAID Module RMS25CB040 Intel(R) Integrated RAID Module RMT3CB080 Intel(R) Integrated RAID Module RMS25JB080 Intel(R) Integrated RAID Module RMS25JB040 Intel(R) Integrated RAID Module RMS25KB080 Intel(R) Integrated RAID Module RMS25KB040 Help Text: Comments: Informati
Intel®Server Board S1200V3RP TPS BIOS Setup Interface It also includes a selection option to go to the NIC Configuration screen. To access this screen from the Main screen, select Advanced > PCI Configuration. To move to another screen, press the key to return to the Advanced screen, then select the desired screen. Figure 25. PCI Configuration Screen Screen Field Descriptions: 1.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Back to [PCI Configuration Screen] — [Advanced Screen] — [Screen Map] 2. Memory Mapped I/O above 4 GB Option Values: Enabled Disabled Help Text: Enable or disable memory mapped I/O of 64-bit PCI devices to 4 GB or greater address space. Comments: When enabled, PCI/PCIe Memory Mapped I/O for devices capable of 64-bit addressing is allocated to address space above 4GB, in order to allow larger allocations and avoid impacting address space below 4G.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Comments: When disabled, the system requires an add-in video card or Processor Integrated graphics for the video to be seen. When there is no add-in video card or Processor Integrated graphics installed, Onboard Video is set to Enabled and grayed out so it cannot be changed. Back to [PCI Configuration Screen] — [Advanced Screen] — [Screen Map] 5.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Notes: This configuration page is not visible on some SKU. Back to [PCI Configuration Screen] — [Advanced Screen] — [Screen Map] 9.4.2.8 NIC Configuration The NIC Configuration screen allows the user to configure the NIC controller options for BIOS POST. It also displays the NIC MAC Addresses currently in use. This NIC Configuration screen handles network controllers built in on the baseboard (“onboard”) or installed as an IO Module (IOM).
Intel®Server Board S1200V3RP TPS BIOS Setup Interface affect the Option ROM settings, which depend on the aggregate capabilities of all installed Onboard and IO Module NICs. For each NIC port which is present on an Onboard NIC or IO Module other than InfiniBand controllers, there will be a port-specific PXE Boot enabling option and a MAC Address display. Onboard NICs and NIC ports also have enable/disable options. IO Modules and the ports on them cannot be disabled by BIOS.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Figure 26. NIC Configuration Screen Screen Field Descriptions: 1. Wake on LAN (PME) 126 Revision 1.
Intel®Server Board S1200V3RP TPS Option Values: BIOS Setup Interface Enabled Disabled Help Text: Enables or disables PCI PME function for Wake on LAN capability from LAN adapters. Comments: Enables/disables PCI/PCIe PME# signal to generate Power Management Events (PME) and ACPI Table entries required for Wake on LAN (WOL). However, note that this will enable WOL only with an ACPI-capable Operating System which has the WOL function enabled.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Comments: This selection is to enable/disable the 10GbE PXE Option ROM that is used by all Onboard and IO Module 10 GbE controllers. This option is grayed out and not accessible if the iSCSI Option ROM is enabled or the 10 GbE FCoE Option ROM is enabled. It can co-exist with the 1 GbE PXE Option ROM or with an InfiniBand controller Option ROM.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Enable/Disable Onboard/IOM NIC iSCSI Option ROM Load. Comments: This selection is to enable/disable the iSCSI Option ROM that is used by all Onboard and IO Module 1 GbE and 10 GbE controllers. This option is grayed out and not accessible if the 1 GbE or 10GbE PXE Option ROM is enabled or if the 10 GbE FCoE Option ROM is enabled. It can co-exist with an InfiniBand controller Option ROM.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Intel(R) 82599 Dual-Port 10 Gigabit SFP+ Module Mellanox* ConnectX-3* Single-Port InfiniBand FD14 Module Help Text: Comments: Information only. This is a display showing which Network Controllers on IO Modules are installed on the baseboard. Each of these IO Module NICs will be followed by a section including a group of options that are specific to the type of NIC, either as an Ethernet controller or an InfiniBand controller.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface 14. IOM2 InfiniBand Option ROM Option Values: Enabled Disabled Help Text: Enable/Disable InfiniBand Controller Option ROM and FlexBoot. Comments: This option will control whether the associated InfiniBand Controller Option ROM is executed by BIOS during POST. This will also control whether the InfiniBand controller FlexBoot program appears in the list of bootable devices. This option only appears for Onboard or IO Module InfiniBand controllers.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS 26. IOM2 Port3 PXE 27. IOM2 Port4 PXE Option Values: Enabled Disabled Help Text: Enable/Disable Onboard/IOM NIC Port PXE Boot Comments: This will enable or disable PXE Boot capability for Port of Onboard NIC or IO Module. This option will not appear for ports on a NIC which is Disabled, or for individual ports when the corresponding NIC Port is disabled.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface 36. IOM2 Port3 MAC Address 37. IOM2 Port4 MAC Address Option Values: Help Text: Comments: Information only. 12 hex digits of the MAC address of Port1- Port4 of the Network Controller corresponding to NIC1, NIC2, IOM1, or IOM2. This display will appear only for ports which actually exist on the corresponding Network Controller. If the Network Controller or port is disabled, the port MAC Address will not appear.
BIOS Setup Interface Option Values: Intel®Server Board S1200V3RP TPS Enabled Disabled Help Text: Enable or Disable Serial port A. Comments: Serial Port A can be used for either Serial Over LAN or Serial Console Redirection. Back to [Serial Port Configuration Screen] — [Screen Map] 2. Address Option Values: 3F8h 2F8h 3E8h 2E8h Help Text: Select Serial port A base I/O address. Comments: Legacy I/O port address. This field should not appear when Serial A port enable/disable does not appear.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Help Text: Enable or Disable Serial port B. Comments: Serial Port B can be used for Serial Console Redirection. Back to [Serial Port Configuration Screen] — [Screen Map] 5. Address Option Values: 3F8h 2F8h 3E8h 2E8h Help Text: Select Serial port B base I/O address. Comments: Legacy I/O port address. Back to [Serial Port Configuration Screen] — [Screen Map] 6. IRQ Option Values: 3 4 Help Text: Select Serial port B interrupt request (IRQ) line.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Each USB Mass Storage device may be set to allow the media emulation for which it is formatted, or an emulation may be specified. For USB Flash Memory devices in particular, there are some restrictions: · A USB Key formatted as a CDROM drive will be recognized as an HDD. · A USB Key formatted without a Partition Table will be forced to FDD emulation.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Comments: Information only. Displays the total number of USB devices of all types which have been detected in POST. Note: There is one USB keyboard and one USB mice detected from the BMC KVM function under this item even no USB devices connected to the system. Back to [USB Configuration Screen] — [Screen Map] 2. USB Controller Option Values: Enabled Disabled Help Text: [Enabled] - All on-board USB controllers are turned on and accessible by the OS.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Help Text: Enable/Disable XHCI Pre-Boot Driver support Comments: and inactive. If the USB controller setting is Disabled, this field is grayed out Back to [USB Configuration Screen] — [Screen Map] 5. XHCI Hand-off Option Values: Enabled Disabled Help Text: This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by XHCI driver Comments: and inactive.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface This may be needed for legacy USB keyboard support when using an OS that is USB unaware. Comments: and inactive. If the USB controller setting is Disabled, this field is grayed out Back to [USB Configuration Screen] — [Screen Map] 8. Make USB Devices Non-Bootable Option Values: Enabled Disabled Help Text: Exclude USB in Boot Table. [Enabled]- This will remove all USB Mass Storage devices as Boot options.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS 10. Mass Storage Devices: Option Values: Auto Floppy Forced FDD Hard Disk CD-ROM Help Text: [Auto] - USB devices less than 530 MB are emulated as floppies. [Forced FDD] - HDD formatted drive is emulated as an FDD (e.g., ZIP drive). Comments: This field is hidden if no USB Mass Storage devices are detected. This setup screen can show a maximum of eight USB Mass Storage devices on the screen.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Screen Field Descriptions: 1. Set Throttling Mode Option Values: Auto Help Text: Sets Thermal Throttling mode for memory, to control fans and DRAM power as needed to control DIMM temperatures. [Auto] – Auto Throttling Mode [CLTM] - Closed Loop Thermal Management. [OLTM] - Open Loop Thermal Management. Closed Loop Thermal Management is supported only when ECC DIMM plugged. Open Loop Thermal Management is not supported.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS [Above 1500m](above 4920ft) Optimal performance setting at the highest elevations. Comments: This option sets an altitude value in order to choose a Fan Profile that is optimized for the air density at the current altitude at which the system is installed. Back to [System Acoustic and Performance Configuration] — [Screen Map] 3.
Intel®Server Board S1200V3RP TPS Option Values: BIOS Setup Interface Enabled Disabled Help Text: Enabling this option allows the system fans to operate in Quiet ‘Fan off’ mode while still maintaining sufficient system cooling. In this mode, fan sensors become unavailable and cannot be monitored. There will be limited fan related event generation.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Comments: Back to [System Acoustic and Performance Configuration] — [Screen Map] 2. Ipv4 PXE support Option Values: Enabled Disabled Help Text: Enable Ipv4 PXE Boot Support. If disabled IPV4 PXE boot option will not be created. Comments: Back to [System Acoustic and Performance Configuration] — [Screen Map] 3. Ipv6 PXE support Option Values: Enabled Disabled Help Text: Enable Ipv6 PXE Boot Support.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface soon after power on while the BIOS queries for a Power On Password. Either the Administrator or the User password may be entered for a Power on Password. To access this screen from the Main screen or other top-level “Tab” screen, press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Security screen is selected. Figure 31. Security Screen Screen Field Descriptions: 1.
BIOS Setup Interface Comments: Intel®Server Board S1200V3RP TPS Information only. Indicates the status of the User Password. Back to [Security Screen] — [Screen Map] 3. Set Administrator Password Option Values: [Entry Field – 0-14 characters] Help Text: Administrator password is used if Power On Password is enabled and to control change access in BIOS Setup. Length is 1-14 characters. Case sensitive alphabetic, numeric and special characters !@#$%^&*()-_+=? are allowed.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Help Text: User password is used if Power On Password is enabled and to allow restricted access to BIOS Setup. Length is 1-14 characters. Case sensitive alphabetic, numeric and special characters !@#$%^&*()-_+=? are allowed. Note: Removing the administrator password also removes the user password. Comments: The User password is available only if the Administrator Password has been installed. This option protects Setup settings as well as boot choices.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS must be controlled via a system management interface, and the NMI Diagnostic Interrupt is not available. Note: This option is not visible on S1200V3RP Server Board. Back to [Security Screen] — [Screen Map] 7. TPM State Option Values: May be: Enabled & Activated Enabled & Deactivated Disabled & Activated Disabled & Deactivated Help Text: Comments: Information only. Shows the current TPM device state.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface [Turn On] - Enables and activates TPM. [Turn Off] - Disables and deactivates TPM. [Clear Ownership] - Removes TPM ownership & returns TPM to factory default state. Note: setting returns to [No Operation] on every boot. Comments: Any Administrative Control operation selected will require the system to perform a Hard Reset in order to become effective. Note: This option appears only on boards equipped with a TPM.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Figure 32. Server Management Screen Screen Field Descriptions: 1. Assert NMI on SERR Option Values: Enabled Disabled Help Text: On SERR, generate an NMI and log an error. Note: [Enabled] must be selected for the Assert NMI on PERR setup option to be visible. Comments: This option allows the system to generate an NMI when an SERR occurs, which is a method Legacy Operating System error handlers may use instead of processing a Machine Check.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Back to [Server Management Screen] — [Screen Map] 2. Assert NMI on PERR Option Values: Enabled Disabled Help Text: On PERR, generate an NMI and log an error. Note: This option is only active if the Assert NMI on SERR option has [Enabled] selected. Comments: This option allows the system to generate an NMI when a PERR occurs, which is a method Legacy Operating System error handlers may use instead of processing a Machine Check.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS System action to take on AC power loss recovery. [Stay Off] - System stays off. [Last State] - System returns to the same state before the AC power loss. [Power On] - System powers on. Comments: This option controls the policy that the BMC will follow when AC power is restored after an unexpected power outage.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Note: This Power Restore Delay option applies only to powering on when AC is applied. It has no effect on powering the system up using the Power Button on the Front Panel. A DC power on using the Power Button is not delayed. The purpose of this delay is to avoid having all systems draw “startup surge” power at the same time. Different systems or racks of systems can be set to different delay times to spread out the startup power draws.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS 8. FRB-2 Enable Option Values: Enabled Disabled Help Text: Fault Resilient Boot (FRB). BIOS programs the BMC watchdog timer for approximately 6 minutes. If BIOS does not complete POST before the timer expires, the BMC will reset the system. Comments: This option controls whether the system will be reset if the BMC Watchdog Timer detects what appears to be a hang during POST.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface enabled. When the timer expires without having been reset or turned off, the system will either reset or power off repeatedly. Back to [Server Management Screen] — [Screen Map] 10. OS Boot Watchdog Timer Policy Option Values: Power off Reset Help Text: If the OS watchdog timer is enabled, this is the system action taken if the watchdog timer expires. [Reset] - System performs a reset. [Power Off] - System powers off.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS If enabled, the BMC will be detectable by OSes which support plug and play loading of an IPMI driver. Do not enable this option if your OS does not support this driver. Comments: This option controls whether the OS Server Management Software will be able to find the BMC and automatically load the correct IPMI support software for it. If your OS does not support Plug & Play for the BMC, you will not have the correct IPMI driver software loaded.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Comments: Selection only. Select this line and press the key to go to the System Information group of configuration settings. Back to [Server Management Screen] — [Screen Map] 16. BMC LAN Configuration Option Values: Help Text: View/Configure BMC LAN and user settings. Comments: Selection only. Select this line and press the key to go to the BMC LAN Configuration group of configuration settings.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Screen Field Descriptions: 1. Console Redirection Option Values: Disabled Serial Port A Serial Port B Help Text: Console redirection allows a serial port to be used for server management tasks. [Disabled] - No console redirection. [Serial Port A] - Configure serial port A for console redirection. Enabling this option will disable display of the Quiet Boot logo screen during POST.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface handshake is a relatively conservative protocol which can usually be configured at both ends. When Console Redirection is set to Disabled, this option will be grayed out and unavailable. Back to [Console Redirection Screen] — [Server Management Screen] — [Screen Map] 3. Baud Rate Option Values: 9.6k 19.2k 38.4k 57.6k 115.2k Help Text: Serial port transmission speed. This setting must match the remote terminal application.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS When Console Redirection is set to Disabled, this option will be grayed out and unavailable. Back to [Console Redirection Screen] — [Server Management Screen] — [Screen Map] 5. Legacy OS Redirection Option Values: Enabled Disabled Help Text: This option enables legacy OS redirection (i.e., DOS) on serial port. If it is enabled, the associated serial port is hidden from the legacy OS.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Figure 34. System Information Screen Screen Field Descriptions: 1. Board Part Number Option Values: Help Text: Comments: Information only. Back to [System Information Screen] — [Server Management Screen] — [Screen Map] 2. Board Serial Number Option Values: Help Text: Comments: Information only. Back to [System Information Screen] — [Server Management Screen] — [Screen Map] 3.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Back to [System Information Screen] — [Server Management Screen] — [Screen Map] 4. System Serial Number Option Values: Help Text: Comments: Information only. Back to [System Information Screen] — [Server Management Screen] — [Screen Map] 5. Chassis Part Number Option Values: Help Text: Comments: Information only.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface 9. ME Firmware Revision Option Values: Help Text: Comments: Information only. Back to [System Information Screen] — [Server Management Screen] — [Screen Map] 10. SDR Revision Option Values: Help Text: Comments: Information only. Back to [System Information Screen] — [Server Management Screen] — [Screen Map] 11.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS the Baseboard LAN configuration and the Intel® RMM4 with Dedicated Server Management NIC Module. IP addresses for either IPv4 or IPv6 addressing can be assigned by static IP addresses manually typed in, or by dynamic IP addresses supplied by a Dynamic Host Configuration Protocol (DHCP) server. IPv6 addressing can also be provided by “stateless autoconfiguration” which does not require a DHCP server.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Figure 35. BMC LAN Configuration Screen Screen Field Descriptions: 1. IP Source Option Values: Static Dynamic Help Text: Revision 1.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Select BMC IP Source: If [Static], IP parameters may be edited. If [Dynamic], these fields are display-only and IP address is acquired automatically (DHCP). Comments: This specifies the IP Source for IPv4 addressing for the Baseboard LAN. There is a separate IP Source field for the Intel® RMM4 LAN configuration.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface When IPv6 addressing is enabled, this field is grayed out and inactive. Back to [BMC LAN Configuration Screen] — [Server Management Screen] — [Screen Map] 4. Gateway IP Option Values: [Entry Field 0.0.0.0, 0.0.0.0 is default] Help Text: View/Edit Gateway IP. Press to edit. Comments: This specifies the IPv4 addressing Gateway IP for the Baseboard LAN. There is a separate IPv4 Gateway IP field for the Intel® RMM4 LAN configuration.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Auto Help Text: Select BMC IPv6 source: If [Static], IPv6 parameters may be edited. If [Dynamic], these fields are display-only and IPv6 address is acquired automatically (DHCP). If [Auto], these fields are display-only and IPv6 address is acquired using ICMPv6 router / neighbor discovery. Comments: This specifies the IP Source for IPv6 addressing for the Baseboard LAN configuration.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface View/Edit Gateway IPv6 address. Press to edit. Gateway IPv6 addresses consist of 8 hexadecimal 4 digit numbers separated by colons. Comments: This specifies the Gateway IPv6 Address for the Baseboard LAN. There is a separate Gateway IPv6 Address field for the Intel® RMM4 LAN configuration. This option is only visible when the IPv6 option is set to Enabled. When IPv6 addressing is used, the initial value for this field is acquired from the BMC.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS When an Intel® RMM4 + DMN is installed, the options for Intel® RMM4 LAN Configuration will be visible. When IPv6 is Disabled, the IPv4 configuration fields will be visible and the IPv6 configuration fields will not be visible. When IPv6 is Enabled, the IPv4 fields will be grayed out and inactive, while the IPv6 Configuration fields will be visible.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Back to [BMC LAN Configuration Screen] — [Server Management Screen] — [Screen Map] 13. Subnet Mask Option Values: [Entry Field 0.0.0.0, 0.0.0.0 is default] Help Text: View/Edit Subnet Mask. Press to edit. Comments: This specifies the IPv4 addressing Subnet Mask for the Intel® RMM4 DMN LAN. There is a separate IPv4 Subnet Mask field for the Baseboard LAN configuration.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Help Text: Select Intel(R) RMM4 IPv6 source: If [Static], IPv6 parameters may be edited. If [Dynamic], these fields are display-only and IPv6 address is acquired automatically (DHCP). If [Auto], these fields are display-only and IPv6 address is acquired using ICMPv6 router / neighbor discovery. Comments: This specifies the IP Source for IPv6 addressing for the Intel® RMM4 DMN LAN configuration.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface View/Edit Gateway IPv6 address. Press to edit. Gateway IPv6 addresses consist of 8 hexadecimal 4 digit numbers separated by colons. Comments: This specifies the Gateway IPv6 Address for the Intel® RMM4 DMN LAN. There is a separate Gateway IPv6 Address field for the Baseboard LAN configuration. This option is only visible when the IPv6 option is set to Enabled.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS If none of the IP/IPv6 Source fields is set to Dynamic, then this BMC DHCP Host Name field will be grayed out and inactive. Back to [BMC LAN Configuration Screen] — [Server Management Screen] — [Screen Map] 20. User ID Option Values: anonymous root User3 User4 User5 Help Text: Select the User ID to configure: User1 (anonymous), User2 (root), and User3/4/5 are supported. Comments: These 5 User IDs are fixed choices and cannot be changed.
Intel®Server Board S1200V3RP TPS Option Values: BIOS Setup Interface Enabled Disabled Help Text: Enable / Disable LAN access for selected user. Also enables/disables SOL, KVM, and media redirection. Comments: Note that status setting is Disabled by default until set to Enabled. Back to [BMC LAN Configuration Screen] — [Server Management Screen] — [Screen Map] 23. User Name Option Values: [Entry Field, 4 - 15 characters] Help Text: Press to edit User Name.
BIOS Setup Interface 9.4.2.18 Intel®Server Board S1200V3RP TPS Boot Options Screen (Tab) The Boot Options screen displays all bootable media encountered during POST, and allows the user to configure the desired order in which boot devices are to be tried. To access this screen from the Main screen or other top-level “Tab” screen, press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Boot Options screen is selected.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Figure 36. Boot Option Screen Screen Field Descriptions: 1. System Boot Timeout Option Values: [Entry Field 0 – 65535, 0 is default] Help Text: The number of seconds BIOS will pause at the end of POST to allow the user to press the [F2] key for entering the BIOS Setup utility. Valid values are 0-65535. Zero is the default. A value of 65535 causes the system to go to the Boot Manager menu and wait for user input for every system boot.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS This timeout value is independent of the FRB2 setting for BIOS boot failure protection. The FBR2 countdown will be suspended during the time that the Boot Timeout countdown is active. Also, if the key is pressed during the time that the Boot Timeout is active, the Boot Timeout countdown will be suspended until the Pause state has been dismissed and normal POST processing has resumed. Back to [Boot Options Screen] — Back to [Screen Map] 2.
Intel®Server Board S1200V3RP TPS Option Values: BIOS Setup Interface Help Text: Set the order of the legacy devices in this group. Comments: Selection only. Select this line and press the key to go to the Hard Disk Order Screen. This option appears when one or more bootable Hard Disk drives are available in the system. This includes USB Hard Disk devices and USB Keys formatted for Hard Disk or CRDOM emulation. Back to [Boot Options Screen] — Back to [Screen Map] 7.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Help Text: Set the order of the legacy devices in this group. Comments: Selection only. Select this line and press the key to go to the BEV Device Order Screen. This option appears when one or more bootable BEV Devices are available in the system. Back to [Boot Options Screen] — Back to [Screen Map] 10. Add EFI Boot Option Option Values: Help Text: Add a new EFI boot option to the boot order. Comments: Selection only.
Intel®Server Board S1200V3RP TPS Comments: non EFI aware OS. BIOS Setup Interface If this option is enabled, the system will not boot successfully to a Back to [Boot Options Screen] — Back to [Screen Map] 13. Use Legacy Video for EFI OS Option Values: Enabled Disabled Help Text: If enabled, the BIOS uses the legacy video ROM instead of the EFI video ROM. Comments: This option appears only when EFI Optimized Boot is enabled. Back to [Boot Options Screen] — Back to [Screen Map] 14.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Comments: This option enables or disables the “USB Reorder” functionality. USB Boot Priority, if enabled, is intended for the case where a user wants to be able to plug in a USB device and immediately boot to it, for example in case of a maintenance or System Administration operation. If a User Password is installed, USB Boot Priority action is suspended when a User Password is installed. Back to [Boot Options Screen] — Back to [Screen Map] 16.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Back to [Boot Options Screen] — Back to [Screen Map] 9.4.2.19 CDROM Order The CDROM Order screen allows the user to control the order in which BIOS attempts to boot from the CDROM drives installed in the system. This screen is only available when there is at least one CDROM device available in the system configuration. Note: A USB attached CDROM device will appear in this section.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS To access this screen from the Main screen, select Boot Options > Hard Disk Order. To move to another screen, press the key to return to the Boot Options screen, then select the desired screen. Figure 38. Hard Disk Order Screen Screen Field Descriptions: 1. Hard Disk #1 2. Hard Disk #2 Option Values: Help Text: Set system boot order by selecting the boot option for this position.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Figure 39. Floppy Order Screen Screen Field Descriptions: 1. Floppy Disk #1 2. Floppy Disk #2 Option Values: Help Text: Set system boot order by selecting the boot option for this position. Comments: Choose the order of booting among Floppy Disk devices by choosing which available Floppy Disk device should be in each position in the order. Back to [Floppy Order Screen] — [Boot Options Screen] — [Screen Map] 9.4.2.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS 1. Network Device #1 2. Network Device #2 Option Values: Help Text: Set system boot order by selecting the boot option for this position. Comments: Choose the order of booting among Network Devices by choosing which available Network Device should be in each position in the order. Back to [Network Device Order Screen] — [Boot Options Screen] — [Screen Map] 9.4.2.
Intel®Server Board S1200V3RP TPS 9.4.2.24 BIOS Setup Interface Add EFI Boot Option The Add EFI Boot Option screen allows the user to add an EFI boot option to the boot order. This screen is only available when there is at least one EFI bootable device present in the system configuration. The “Internal EFI Shell” Boot Option is permanent and cannot be added or deleted. To access this screen from the Main screen, select Boot Options > Add EFI Boot Option.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS Option Values: [Enter Boot Path] Help Text: Enter the path to the boot option in the format \path\filename.efi. Comments: This will be the Boot Path, residing on the filesystem chosen, which will enter into the Boot Order with the Label entered above. Back to [Add EFI Boot Option Screen] — [Boot Options Screen] — [Screen Map] 4. Save Option Values: Help Text: Save the boot option. Comments: Order. Selection only.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Select one to delete. Comments: This will not allow a user to delete the EFI Shell. Back to [Delete EFI Boot Option Screen] — [Boot Options Screen] — [Screen Map] 9.4.2.26 Boot Manager Screen (Tab) The Boot Manager screen allows the user to view a list of devices available for booting, and to select a boot device for immediately booting the system. There is no predetermined order for listing bootable devices.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS 2. 3. 4. Option Values: Help Text: Select this option to boot now. Note: This list is not the system boot option order. Use the Boot Options menu to view and configure the system boot option order. Comments: These are names of bootable devices discovered in the system.
Intel®Server Board S1200V3RP TPS Help Text: BIOS Setup Interface Comments: This is a POST Error Code – a BIOS-originated error that occurred during POST initialization. Back to [Error Manager Screen] — [Screen Map] 2. SEVERITY Option Values: Minor Major Fatal Help Text: Comments: Each POST Error Code has a Severity associated with it. Back to [Error Manager Screen] — [Screen Map] 3.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS are applied. If Load User Default Values is selected, the system is restored to previously saved User Default Values. To access this screen from the Main screen or other top-level “Tab” screen, press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Exit screen is selected.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface If changes have been made in BIOS settings, a confirmation pop-up will appear. If the “Save Changes & Exit” action is positively confirmed, any persistent changes will applied and saved to the BIOS settings in NVRAM storage, then the system will reboot if necessary (which is normally the case). If the “Save Changes & Exit” action is not confirmed, BIOS will resume executing Setup.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS 4. Discard Changes Option Values: Help Text: Discard Changes made so far to any of the setup options. Comments: Selection only. Select this line and press the key to discard any pending unsaved changes in BIOS settings. If there have been no changes made in the settings, the BIOS will resume executing POST. If changes have been made in BIOS settings and not yet saved, a confirmation pop-up will appear.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface Comments: Selection only. Select this line and press the key to save the current state of the settings for all BIOS parameters as a customized set of “User Default Values”. These are a user-determined set of BIOS default settings that can be used as an alternative instead of the initial factory settings (“failsafe” settings) for all BIOS parameters.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS The BIOS update is done using a “capsule” file which contains all relevant BIOS components. This capsule omits the NVRAM Firmware Volume, which retains its existing contents through the BIOS Update. There is a single BIOS capsule file for a given BIOS Release for updating the BIOS on all of the boards in the S1200RP Server Board Family.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface If the flash update fails for reasons of security compliance, a different message will be displayed: Error: BIOS or ME update failure - the capsule file failed in the security compliance check. Please refer to BIOS Release Notes for details. 7. In order to properly complete the BIOS Update process, the system must perform a shutdown – DC power-off – then DC power-on and boot successfully to the EFI Shell or an OS environment.
BIOS Setup Interface 9.5.3 Intel®Server Board S1200V3RP TPS BIOS Backup Flash Update The BIOS is also supported for updating the backup BIOS regions by update utility issues “UpdateBackupBios” command. After the BIOS receives request from utility, the backup BIOS update will be completed in next normal boot. It will show message "DO NOT REMOVE POWER! Now updating Backup BIOS region......" in update beginning, after backup update completed, will show “Done”.
Intel®Server Board S1200V3RP TPS BIOS Setup Interface The Recovery procedure is included here for general reference. However, if in conflict, the instructions in the BIOS Release Notes are the definitive version. A BIOS recovery can be accomplished with images on backup flash blocks. The Recovery medium in USB Flash Drive must contain the following files in its root directory: UEFI iFlash32 (including IFlash32.efi and ipmi.efi) *Rec.
BIOS Setup Interface Intel®Server Board S1200V3RP TPS 8. Power off the system. Again, removing AC power is not necessary but may be advisable due to safety considerations, or if a riser or other hardware must be moved for access to the BIOS Recovery jumper. 9. Open the chassis, move hardware if necessary, and restore the recovery jumper position to "normal operation" pins 1-2. Replace any hardware moved, and close the chassis. 10. Remove Recovery medium. 11.
Intel®Server Board S1200V3RP TPS Jumper Blocks 10. Jumper Blocks The server board includes several 3-pin jumper blocks which are used to as part of a process to restore a board function back to a normal functional state. The following diagram and sections identify the location of each jumper block and provides a description of their use. The following symbol identifies Pin 1 on each jumper block on the silkscreen: Figure 47. Jumper Blocks (J2K6, J2K8, J2K9, J3K2, J3K6) Note: 1.
Jumper Blocks Intel®Server Board S1200V3RP TPS Table 58. Server Board Jumpers (J2K6, J2K8, J2K9, J3K2, J3K6) Jumper Name J2K6: BIOS Default Pins 1-2 System Results These pins should have a jumper in place for normal system operation. (Default) 2-3 If pins 2-3 are jumpered with AC power plugged in, the CMOS settings clear in 5 seconds. Pins 2-3 should not be jumpered for normal system operation. J2K8: BIOS Recovery 1-2 Pins 1-2 should be jumpered for normal system operation.
Intel®Server Board S1200V3RP TPS Jumper Blocks 1. After downloading the latest System Update Package (SUP) from the Intel® website, copy the following files to the root directory of a USB media device: IPMI.EFI IFlash32.EFI RML.ROM ####REC.CAP (where #### = BIOS revision number) STARTUP.NSH 2. Power OFF the system 3. Locate the BIOS Recovery Jumper on the server board and move the jumper block from pins 1-2 (default) to pins 2-3 (recovery setting) 4. Insert the recovery media into a USB port 5.
Jumper Blocks Intel®Server Board S1200V3RP TPS Note: BIOS Error Manager should report a 5224 and 5221 error codes (Password clear jumper is set and Passwords cleared by jumper). 6. Power down the server and unplug the power cords. 7. Open the chassis, remove the Riser #2 assembly, and move the jumper back to the default position (covering pins 1 and 2). 8. Reinstall the Riser #2 assembly. 9. Close the server chassis and reattach the power cords. 10. Power up the server. 10.
Intel®Server Board S1200V3RP TPS Jumper Blocks 10. Install PCI Riser. 11. Install AC power cords. 12. Power on system. 10.5 BMC Force Update Jumper Block The BMC Force Update jumper is used to put the BMC in Boot Recovery mode for a low-level update. It is used when the BMC has become corrupted and is non-functional, requiring a new BMC image to be loaded on to the server board. 1. Turn off the system and remove power cords. 2.
Intel®Light Guided Diagnostics Intel®Server Board S1200V3RP TPS 11. Intel®Light Guided Diagnostics The server board includes several on-board LED indicators to aid troubleshooting various board level faults. The following figure shows the location for each: Figure 48. On-Board LED Placement 206 Revision 1.
Intel®Server Board S1200V3RP TPS Intel®Light Guided Diagnostics 11.1 System ID LED The server board includes a blue system ID LED which is used to visually identify a specific server installed among many other similar servers. There are two options available for illuminating the System ID LED. 1. The front panel ID LED Button is pushed, which causes the LED to illuminate to a solid on state until the button is pushed again. 2.
Intel®Light Guided Diagnostics Color State Intel®Server Board S1200V3RP TPS Criticality Description failed/disabled but functional memory remains available) Correctable Errors over a threshold and migrating to a spare DIMM (memory sparing). This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition. Corresponding DIMM LED lit. Uncorrectable memory error has occurred in memory Mirroring Mode, causing Loss of Redundancy.
Intel®Server Board S1200V3RP TPS Color State Intel®Light Guided Diagnostics Criticality Description 240VA fault Fatal Error in processor initialization: Processor family not identical Processor model not identical Processor core/thread counts not identical Processor cache size not identical Unable to synchronize processor frequency Unable to synchronize QPI link frequency 11.
Intel®Light Guided Diagnostics Intel®Server Board S1200V3RP TPS 11.5 5 Volt Stand-By Present LED This LED is illuminated when a power cord (AC or DC) is connected to the server and the power supply is supplying 5 Volt Stand-by power to the server board. This LED is intended as a service caution indicator to anyone accessing the inside of the server system. 210 Revision 1.
Intel®Server Board S1200V3RP TPS Environmental Limits Specification 12. Environmental Limits Specification The following table defines the Intel® Server Board S1200V3RP series operating and nonoperating environmental limits. Operation of the Intel® Server Board S1200V3RP at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 61.
Environmental Limits Specification Intel®Server Board S1200V3RP TPS the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions.
Intel®Server Board S1200V3RP TPS Server Board Power Distribution 13. Server Board Power Distribution This section provides power supply design guidelines for a system using the Intel® Server Board S1200V3RP. The following diagram shows the power distribution implemented on this server board. The power supply data provided in this section is for reference purposes only. It reflects Intel’s own DC power out requirements for a 365W power supply as used in an Intel designed 4U server platform.
Server Board Power Distribution Parameter 5Vstby Note: 1. Intel®Server Board S1200V3RP TPS Min Max. 0.0 Peak 2.5 3.0 Max combined power for all output shall not exceed 350W. 2. Peak combined power for all outputs shall not exceed 400W. 3. Max combined power of 12V1 and 12V2 shall not exceed 318W. 4. Max combined power on 3.3V and 5V shall not exceed 100W. 5. Peak power and current loading shall be supported for a minimum of 12 second. 13.1.
Intel®Server Board S1200V3RP TPS 13.1.5 Server Board Power Distribution Dynamic Loading The output voltages remain within limits specified for the step loading and capacitive loading specified in the table below. The load transient repetition rate is tested between 50Hz and 5kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The step load may occur anywhere within the MIN load to the MAX load conditions. Table 66.
Server Board Power Distribution Intel®Server Board S1200V3RP TPS The residual voltage at the power supply outputs for no load condition does not exceed 100mV when AC voltage is applied and the PSON# signal is de-asserted. 13.1.9 Common Mode Noise The Common Mode noise on any output does not exceed 350mV pk-pk over the frequency band of 10Hz to 20MHz.
Intel®Server Board S1200V3RP TPS Server Board Power Distribution shows the timing requirements for the power supply being turned on and off from the AC input, with PSON held low and the PSON signal, with the AC input applied. Table 69. Output Voltage Timing Item Tvout_rise Description Output voltage rise time from each main output. 2 MIN 50 MAX ms UNITS Output rise time for the 5Vstby output. 1 25 ms Tvout_on All main outputs must be within regulation of each other within this time.
Server Board Power Distribution Intel®Server Board S1200V3RP TPS Item T pson_pwok Description Delay from PSON# deactivate to PWOK being de-asserted. Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on. 100 T pwok_off Delay from PWOK de-asserted to output voltages (3.3V, 5V, 12V, -12V) dropping out of regulation limits. 1 Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal.
Intel®Server Board S1200V3RP TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips When adding or removing components or peripherals from the server board, you must remove AC power cord. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off. This server board supports Intel® Xeon® Processor E3-1200 V3 product family with a Thermal Design Power (TDP) of up to and including 95 Watts.
Appendix B: Integrated BMC Sensor Tables Intel®Server Board S1200V3RP TPS Appendix B: Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.
Intel®Server Board S1200V3RP TPS Appendix B: Integrated BMC Sensor Tables - A: Auto-rearm - M: Manual rearm Default Hysteresis The hysteresis setting applies to all thresholds of the sensor. This column provides the count of hysteresis for the sensor, which is 1 or 2 (positive or negative hysteresis). Criticality Criticality is a classification of the severity and nature of the condition. It also controls the behavior of the Control Panel Status LED.
Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Se ns or # Platform Applicabilit y (IPMI Watchdog) Sensor Type 23h Event/R eading Type c 6Fh Intel®Server Board S1200V3RP TPS Event Offset Triggers Contrib.
Intel®Server Board S1200V3RP TPS Full Sensor Name (Sensor name in SDR) Se ns or # Platform Applicabilit y Sensor Type Appendix B: Integrated BMC Sensor Tables Event/R eading Type Event Offset Triggers Sufficient resources. Transition from redundant Contrib. To System Status Assert /Deassert Reada ble Event Data Rearm St an db y Value/ Offset s ed 04 - Non-redundant: Sufficient resources. Transition from insufficient. Degrad ed 05 - Non-redundant: insufficient resources.
Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard Temperature 6 (Platform Specific) IO Module2 Temperature (I/O Mod2 Temp) PCI Riser 3 Temperature (PCI Riser 5 Temp) PCI Riser 4 Temperature (PCI Riser 4 Temp) Baseboard +1.05V Processor3 Vccp (BB +1.05Vccp P3) Baseboard +1.05V Processor4 Vccp (BB +1.
Intel®Server Board S1200V3RP TPS Full Sensor Name (Sensor name in SDR) SSB Temperature (SSB Temp) Baseboard Temperature 2 (Platform Specific) Baseboard Temperature 3 (Platform Specific) Baseboard Temperature 4 (Platform Specific) IO Module Temperature (I/O Mod Temp) PCI Riser 1 Temperature (PCI Riser 1 Temp) IO Riser Temperature (IO Riser Temp) Se ns or # 22 h 23 h 24 h 25 h 26 h 27 h 28 h Platform Applicabilit y All Platformspecific Sensor Type Temper ature 01h Temper ature 01h Appendix
Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Se ns or # Temperature (HSBP 2 Temp) h Hot-swap Backplane 3 Temperature (HSBP 3 Temp) PCI Riser 2 Temperature (PCI Riser 2 Temp) SAS Module Temperature (SAS Mod Temp) Exit Air Temperature (Exit Air Temp) 2 B h 2 C h Platform Applicabilit y Sensor Type 01h Chassisspecific Platformspecific 2 D h Platformspecific 2 E h Chassis and Platform Specific Temper ature 01h Temper ature 01h Temper ature 01h Temper ature
Intel®Server Board S1200V3RP TPS Full Sensor Name (Sensor name in SDR) Power Supply 2 Status (PS2 Status) Power Supply 1 AC Power Input (PS1 Power In) Power Supply 2 AC Power Input (PS2 Power In) Power Supply 1 +12V % of Maximum Current Output (PS1 Curr Out %) Power Supply 2 +12V % of Maximum Current Output (PS2 Curr Out %) Se ns or # 51 h 54 h 55 h 58 h 59 h Platform Applicabilit y Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Sensor Type Power Supply 08h
Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Se ns or # Platform Applicabilit y Sensor Type Supply 2 Temperature (PS2 Temperature ) D h specific ature Hard Disk Drive 16 - 24 Status (HDD 16 24 Status) 60 h – 68 h Chassisspecific Drive Slot 0Dh Intel®Server Board S1200V3RP TPS Event/R eading Type Event Offset Triggers Contrib.
Intel®Server Board S1200V3RP TPS Full Sensor Name (Sensor name in SDR) Se ns or # Platform Applicabilit y Thermal Margin (P4 Therm Margin) h specific Processor 1 Thermal Control % (P1 Therm Ctrl %) Processor 2 Thermal Control % (P2 Therm Ctrl %) Processor 3 Thermal Control % (P3 Therm Ctrl %) 78 h 79 h 7 A h All All Platformspecific Sensor Type ature 01h Temper ature 01h Temper ature 01h Temper ature 01h Appendix B: Integrated BMC Sensor Tables Event/R eading Type Event Offset Triggers C
Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Se ns or # MSID Mismatch (P1 MSID Mismatch) h Processor Population Fault (CPU Missing) 82 h Processor 1 DTS Thermal Margin (P1 DTS Therm Mgn) Platform Applicabilit y Sensor Type sor 07h Intel®Server Board S1200V3RP TPS Event/R eading Type Event Offset Triggers Contrib.
Intel®Server Board S1200V3RP TPS Full Sensor Name (Sensor name in SDR) Se ns or # VRD Temperature (P3 VRD Hot) h Processor 4 VRD Temperature (P4 VRD Hot) 93 h Processor 1 Memory VRD Hot 0-1 (P1 Mem01 VRD Hot) 94 h Processor 1 Memory VRD Hot 2-3 (P1 Mem23 VRD Hot) 95 h Processor 2 Memory VRD Hot 0-1 (P2 Mem01 VRD Hot) 96 h Processor 2 Memory VRD Hot 2-3 (P2 Mem23 VRD Hot) 97 h Processor 3 Memory VRD Hot 0-1 (P3 Mem01 VRD Hot) 98 h Processor 3 Memory VRD Hot 2-3 (P4 Mem23 VRD Hot) 99 h Proce
Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Se ns or # Platform Applicabilit y Power Supply 1 Fan Tachometer 1 (PS1 Fan Tach 1) A 0h Chassisspecific Fan 04h Generi c– digital discret e 01 – State Asserted Nonfatal As and De - Power Supply 1 Fan Tachometer 2 (PS1 Fan Tach 2) A 1h Chassisspecific Fan 04h Generi c– digital discret e 01 – State Asserted Nonfatal As and De Chassisspecific Fan 04h Generi c– digital discret e 01 – State Asserted Nonfatal
Intel®Server Board S1200V3RP TPS Full Sensor Name (Sensor name in SDR) Processor 2 DIMM Aggregate Thermal Margin 2 (P2 DIMM Thrm Mrgn2) Processor 3 DIMM Aggregate Thermal Margin 1 (P3 DIMM Thrm Mrgn1) Processor 3 DIMM Aggregate Thermal Margin 2 (P3 DIMM Thrm Mrgn2) Processor 4 DIMM Aggregate Thermal Margin 1 (P4 DIMM Thrm Mrgn1) Se ns or # B 3h B 4h B 5h B 6h Platform Applicabilit y All Platform Specific Platform Specific Platform Specific Sensor Type Temper ature 01h Temper ature 01h Temper
Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Se ns or # Platform Applicabilit y Sensor Type Intel®Server Board S1200V3RP TPS Event/R eading Type Event Offset Triggers Contrib.
Intel®Server Board S1200V3RP TPS Full Sensor Name (Sensor name in SDR) Se ns or # Platform Applicabilit y Margin 6 (Agg Therm Mrgn 6) Sensor Type Appendix B: Integrated BMC Sensor Tables Event/R eading Type 01h 01h Event Offset Triggers Contrib.
Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Se ns or # Platform Applicabilit y Sensor Type Event/R eading Type Intel®Server Board S1200V3RP TPS Event Offset Triggers +1.05Vccp P1) Baseboard +1.05V Processor2 Vccp (BB +1.05Vccp P2) Baseboard +1.5V P1 Memory AB VDDQ (BB +1.5 P1MEM AB) Baseboard +1.5V P1 Memory CD VDDQ (BB +1.5 P1MEM CD) Baseboard +1.5V P2 Memory AB VDDQ (BB +1.5 P2MEM AB) Baseboard +1.5V P2 Memory CD VDDQ (BB +1.5 P2MEM CD) Baseboard +1.8V Aux (BB +1.
Intel®Server Board S1200V3RP TPS Full Sensor Name (Sensor name in SDR) Se ns or # Platform Applicabilit y Sensor Type Appendix B: Integrated BMC Sensor Tables Event/R eading Type Event Offset Triggers Contrib. To System Status Assert /Deassert Reada ble Event Data Rearm St an db y Value/ Offset s fatal Baseboard +1.35V P1 Low Voltage Memory AB VDDQ (BB +1.35 P1LV AB) Baseboard +1.35V P1 Low Voltage Memory CD VDDQ (BB +1.35 P1LV CD) Baseboard +1.35V P2 Low Voltage Memory AB VDDQ (BB +1.
Appendix B: Integrated BMC Sensor Tables 238 Intel®Server Board S1200V3RP TPS 3. Redundancy sensors will be only present on systems with appropriate hardware to support redundancy (for instance, fan or power supply). 4. This is only applicable when the system does not support redundant fans. When fan redundancy is supported, then the contribution to system state is driven by the fan redundancy sensor. Revision 1.
Intel®Server Board S1200V3RP TPS Appendix C: POST Code Diagnostic LED Decoder Appendix C: POST Code Diagnostic LED Decoder As an aid to assist in trouble shooting a system hang that occurs during a system’s Power-On Self Test (POST) process, the server board includes a bank of eight POST Code Diagnostic LEDs on the back edge of the server board.
Appendix C: POST Code Diagnostic LED Decoder Results 1 0 Intel®Server Board S1200V3RP TPS 1 0 Ah 1 1 0 0 Ch Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh The following table provides a list of all POST progress codes. Table 73.
Intel®Server Board S1200V3RP TPS Appendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder 1 = LED On, 0 = LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED # #7 #6 #5 #4 #3 #2 #1 #0 71h 0 1 1 1 0 0 0 1 DXE SB SMM Init Description 72h 0 1 1 1 0 0 1 0 DXE SB devices Init 78h 0 1 1 1 1 0 0 0 DXE ACPI Init 79h 0 1 1 1 1 0 0 1 DXE CSM Init 90h 1 0 0 1 0 0 0 0 DXE BDS Started 91h 1 0 0 1 0 0 0 1 DXE BDS connect drivers
Appendix C: POST Code Diagnostic LED Decoder Intel®Server Board S1200V3RP TPS Diagnostic LED Decoder 1 = LED On, 0 = LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED # #7 #6 #5 #4 #3 #2 #1 #0 S3 Resume Description E0h 1 1 0 1 0 0 0 0 S3 Resume PEIM (S3 started) E1h 1 1 0 1 0 0 0 1 S3 Resume PEIM (S3 boot script) E2h 1 1 0 1 0 0 1 0 S3 Resume PEIM (S3 Video Repost) E3h 1 1 0 1 0 0 1 1 S3 Resume PEIM (S3 OS wake) BIOS Recovery F0h 1
Intel®Server Board S1200V3RP TPS Diagnostic LED Decoder 1 = LED On, 0 = LED Off Upper Nibble Lower Nibble Checkpoint LED BFh Appendix C: POST Code Diagnostic LED Decoder MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h #7 #6 #5 #4 #3 #2 #1 #0 1 0 1 1 1 1 1 1 MRC is done Description Memory Initialization at the beginning of POST includes multiple functions, including: discovery, channel training, validation that the DIMM population is acceptable and functional, initialization of the IMC and other hardware settings, and
Appendix C: POST Code Diagnostic LED Decoder Intel®Server Board S1200V3RP TPS Diagnostic LED Decoder 1 = LED On, 0 = LED Off Checkpoint Upper Nibble Lower Nibble MSB LED Description LSB 8h 4h 2h 1h 8h 4h 2h 1h #7 #6 #5 #4 #3 #2 #1 #0 EDh EFh 244 1 1 1 0 1 1 0 1 DIMM configuration population error 01h = Different DIMM types (UDIMM, RDIMM, LRDIMM) are detected installed in the system. 02h = Violation of DIMM population rules.
Intel®Server Board S1200V3RP TPS Appendix D: POST Code Errors Appendix D: POST Code Errors Most error conditions encountered during POST are reported using POST Error Codes. These codes represent specific failures, warnings, or are informational. POST Error Codes may be displayed in the Error Manager display screen, and are always logged to the System Event Log (SEL). Logged events are available to System Management applications, including Remote and Out of Band (OOB) management.
Appendix D: POST Code Errors Intel®Server Board S1200V3RP TPS Error Code 0146 PCI out of resources error Error Message Response Major 0191 Processor core/thread count mismatch detected Fatal 0192 Processor cache size mismatch detected Fatal 0194 Processor family mismatch detected Fatal Intel® 0195 Processor 0196 Processor model mismatch detected Fatal 0197 Processor frequencies unable to synchronize Fatal 5220 BIOS Settings reset to default settings Major 5221 Passwords cleared b
Intel®Server Board S1200V3RP TPS Appendix D: POST Code Errors Error Code 8527 DIMM_C2 failed test/initialization Response Major 8528 DIMM_C3 failed test/initialization Major 8529 DIMM_D1 failed test/initialization Major 852A DIMM_D2 failed test/initialization Major 852B DIMM_D3 failed test/initialization Major 852C DIMM_E1 failed test/initialization Major 852D DIMM_E2 failed test/initialization Major 852E DIMM_E3 failed test/initialization Major 852F DIMM_F1 failed test/initializa
Appendix D: POST Code Errors Intel®Server Board S1200V3RP TPS Error Code 8553 DIMM_G2 disabled Response Major 8554 DIMM_G3 disabled Major 8555 DIMM_H1 disabled Major 8556 DIMM_H2 disabled Major 8557 DIMM_H3 disabled Major 8558 DIMM_I1 disabled Major 8559 DIMM_I2 disabled Major 855A DIMM_I3 disabled Major 855B DIMM_J1 disabled Major 855C DIMM_J2 disabled Major 855D DIMM_J3 disabled Major 855E DIMM_K1 disabled Major 855F (Go to 85D0) DIMM_K2 disabled Major 8560 DIMM_A
Intel®Server Board S1200V3RP TPS Appendix D: POST Code Errors Error Code 857F (Go to 85E0) Error Message DIMM_K2 encountered a Serial Presence Detection (SPD) failure Response Major 85C0 DIMM_K3 failed test/initialization Major 85C1 DIMM_L1 failed test/initialization Major 85C2 DIMM_L2 failed test/initialization Major 85C3 DIMM_L3 failed test/initialization Major 85C4 DIMM_M1 failed test/initialization Major 85C5 DIMM_M2 failed test/initialization Major 85C6 DIMM_M3 failed test/initi
Appendix D: POST Code Errors Intel®Server Board S1200V3RP TPS Error Code 85EB Error Message DIMM_O2 encountered a Serial Presence Detection (SPD) failure Response Major 85EC DIMM_O3 encountered a Serial Presence Detection (SPD) failure Major 85ED DIMM_P1 encountered a Serial Presence Detection (SPD) failure Major 85EE DIMM_P2 encountered a Serial Presence Detection (SPD) failure Major 85EF DIMM_P3 encountered a Serial Presence Detection (SPD) failure Major 8604 POST Reclaim of non-critical
Intel®Server Board S1200V3RP TPS Appendix D: POST Code Errors Table 78. Integrated BMC Beep Codes Code 1-5-2-1 Reason for Beep No CPUs installed or first CPU socket is empty. Associated Sensors CPU1 socket is empty, or sockets are populated incorrectly CPU1 must be populated before CPU2. 1-5-2-4 MSID Mismatch MSID mismatch occurs if a processor is installed into a system board that has incompatible power capabilities.
Appendix E: Supported Intel®Server Chassis Intel®Server Board S1200V3RP TPS Appendix E: Supported Intel®Server Chassis The Intel® Server Board S1200V3RP requires a passive processor heat sink solution when integrated in the Intel® pedestal server chassis listed below. The Intel® Server Board S1200V3RP supports up to 95W TDP Intel® Xeon® Processor. Table 79.
Intel®Server Board S1200V3RP TPS Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) with alpha entries following (for example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
Glossary Intel®Server Board S1200V3RP TPS Term Definition IBF Input buffer ICH I/O controller hub IERR Internal error INIT Initialization signal IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface ITP In-target probe KCS Keyboard controller style KT Keyboard text KVM Keyboard, video, and mouse LAN Local area network LCD Liquid crystal display LPC Low pin count LUN Logical unit number MAC Media Access Control MD5 Message Digest 5.
Intel®Server Board S1200V3RP TPS Glossary Term SDRAM Definition Synchronous dynamic random access memory SEL System event log SHA1 Secure Hash Algorithm 1 SIO Server Input/Output SMBus* A two-wire interface based on the I2C protocol. The SMBus* is a low-speed bus that provides positive addressing for devices and bus arbitration. SMI Server management interrupt. SMI is the highest priority non-maskable interrupt.
Reference Documents Intel®Server Board S1200V3RP TPS Reference Documents See the following documents for additional information: Advanced Configuration and Power Interface Specification, Revision 5.0, http://www.acpi.info/. Intelligent Platform Management Bus Communications Protocol Specification, Version 1.0. 1998. Intel Corporation, Hewlett-Packard* Company, NEC* Corporation, Dell* Computer Corporation. Intelligent Platform Management Interface Specification, Version 2.0. 2004.
