Datasheet

53
- Software Clarifications—Intel
®
82599 10 GbE Controller
3 Serial Interfaces Programmed by Bit Banging
When bit-banging on a serial interface (such as SPI, I
2
C, or MDIO), it is often necessary to perform
consecutive register writes with a minimum delay between them. However, simply inserting a software
delay between the writes can be unreliable due to hardware delays on the CPU and PCIe interfaces. The
delay at the final hardware interface might be less than intended if the first write is delayed by
hardware more than the second write. To prevent such problems, a register read should be inserted
between the first register write and the software delay, i.e. “write”, “read”, “software delay”, “write”.
4 Identify Network Adapter Port by Blinking LED
Intel device drivers and supported tools include a feature that provides network adapter port
identification by blinking LED2. This feature assumes that LED2 is connected as the Link/Activity LED as
recommended in the reference schematics.
5 PF/VF Drivers Should Configure Registers That Are
not Reset by VFLR
The following registers are not reset by VFLR and need to be configured by PF or VF in case of a change
to a new configuration (such as VF OS transition): VFRDH/T, VFTDH/T, VFPSRTYPE, VFSRRCTL,
VFRXDCTL, VFTXDCTL, VFTDWBAL/H, VFDCA_RXCTRL, VFDCA_TXCTRL.
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