Datasheet

43
Errata—Intel
®
82599 10 GbE Controller
46 PCIe: Correctable Errors Reported When Using Rx
L0s in a x1 Configuration
Problem:
When using Rx L0s in an x1 configuration, the 82599 reports receiver errors at a rate of more than one
per minute on some platforms.
Implication:
Correctable errors are reported at a higher rate than can be explained by random bit errors. These
errors should be ignored by the system.
Workaround:
None.
Status: B0=Yes; NoFix
47 PCIe: N_FTS Value Is too Small When Common
Clock Configuration Is Zero
Problem:
When the Common Clock Configuration bit in the Link Control register is 0b, the value of the N_FTS
advertised by the 82599 is taken from internal configuration registers, with separate values used for
Gen1 and Gen2 speeds. The hardware default values are too small to guarantee a clean exit from L0s
in all cases.
As a result, link recovery procedures might be performed and correctable errors might be reported:
Bad TLP, Bad DLLP, and Replay Timer Timeout.
Note that even on platforms where the Common Clock Configuration bit is set to 1b, this bit is cleared
by hot reset or D3-to-D0 transitions, and the previous situation can still occur until the configuration
space programming has been restored.
Implication:
The correctable errors can generally be ignored. the link recovery procedures and replayed packets
result in a small reduction of effective bandwidth on the PCIe link.
However, in certain circumstances on some platforms, the repeated loss of packets can lead to a
completion timeout error, which might cause the application and/or the system to stop working.
Workaround:
Three workarounds are available:
1. Disable L0s on the upstream device.
2. Disable L0s on the upstream device before putting the 82599 in hot reset or D3 states.
3. Upgrade EEPROM image:
— Use EEPROM version 4.09 or newer.
Status: B0=Yes; NoFix