Datasheet

41
Errata—Intel
®
82599 10 GbE Controller
42 PCIe: 82599 Transmitter Does not Enter L0s
Problem:
According to the PCIe specification “Ports that are enabled for L0s entry must transition their transmit
lanes to the L0s state if the defined idle conditions are met for a period of time not to exceed 7 s”. Due
to how the 82599 was designed, the idle counter does not initiate a L0s transition.
Implication:
PCIe specification compliance issue. The 82599 transmitter does not enter L0s, causing a small
increase in power consumption.
Workaround:
None.
Note: The 82599 EEPROM images have the “L0s Entry Supported” bit set, since some systems
use this configuration as a condition for Tx L0s enablement in the upstream device
transmit side.
Status: B0=Yes; NoFix
43 Integrity Error Reported for IPv4/UDP Packets
with Zero Checksum
Problem:
According to the UDP specification “an all zero transmitted checksum value means that the transmitter
generated no checksum (for debugging or for higher level protocols that don’t care)”, these packets
should be received without a checksum error notation. The 82599 reports an L4 integrity error if such
packets are received.
Implication:
UDP packets without a checksum will have an L4 integrity error indication in the Rx descriptor.
Workaround:
If bits L4E and L4I are set in the Rx descriptor, the software driver should check if the checksum is zero
and then ignore this error.
Status: B0=Yes; NoFix