Datasheet

Intel
®
82599 10 GbE Controller—Errata
30
18 SGMII 100M: 82599 Might Need a SW-Reset When
Link-Mode Enters/Exits 100M
Problem:
On speed changes to or from 100 Mb and for specific traffic timing, clock switching might occur during
traffic resulting in issues in TX path.
Implication:
When transmit path appears un-responsive following a entry/exit to 100M speed, a SW reset is
required.
Workaround:
When working with SGMII 100M enabled and after link-mode changes if there's an indication transmit is
not working, SW should give SW-reset to release the device.
Status: B0=Yes; NoFix
19 DFT: Rx-to-Tx Loopback (XGMII LPBK) in
1Gb\100Mb with Low IPG May Cause Chopped
Packet
Problem:
In XGMII loopback and 1GbE/100 Mb/s speeds, if the IPG is low (the accurate number depends on
XGMII-MUX threshold and system PPM), Tx packets will be chopped.
Implication:
Testing using this mode while in 1GbE/100 Mb/s modes may encounter this problem.
Workaround:
A safe IPG to run with should be higher than 55 bytes.
Status: B0=Yes; NoFix
20 DFT: JTDO Output Is Disabled During HIGHZ
Instruction
Problem:
The 82599 disables JTDO outputs during a HIGHZ instruction. According to IEEE Std 1149.1-2001, “The
HIGHZ instruction shall select the bypass register to be connected for serial access between TDI and
TDO in the Shift-DR controller state.”
Implication:
If multiple devices are chained in the board, the tester won't be able to check devices behind the 82599
when it is in HIGHZ.