Datasheet

Intel
®
82599 10 GbE Controller—Errata
28
13 Issues in Clock Switching of MAC Clocks
Problem:
During changes in the internal link-speed, the timing of the clock-switch might cause problems in the
transmit path.
Implication:
The transmit path might hang.
Workaround:
In SW, set bit 19 of the AUTOC2 register to 1b as part of init flow (through EEPROM/SW). This delays
the link-up flow by 10 µs, allowing a safe clock-switch. Note that Intel drivers expect bit 19 of the
AUTOC2 register to be set by EEPROM.
Status: B0=Yes; NoFix
14 FEC: Correctable and Uncorrectable Counter Read
Mechanism Is Malformed
Problem:
The FEC counters (FECS1 and FECS2) return values only after the read transaction is done.
Implication:
The read result of these counters is available only on the next read request. Since these are set to clear
on read, an extra dummy read causes clearing of the counter without getting the result.
Workaround:
For an independent read: perform two read transactions and ignore the data returned in the first read
transaction.
For continuous reading: keep track of the result (each read will return the result of the previous read of
the CSR).
Status: B0=Yes; NoFix