Datasheet

Intel

82599 10 GbE Controller—Specification Clarifications

9 Master Disable Flow

During the “Master Disable” flow, the device driver should set the PCIe Master Disable bit and then poll

the PCIe Master Enable Status bit to determine if any requests are pending. There are cases where this

bit will not be released (such as flow control or link down), even if the PCIe Transaction Pending bit is

cleared in the Device Status register. In such cases, the recommendation (see Datasheet, search for

“Master Disable”) is to issue two consecutive software resets with a delay larger than 1 microsecond

between them.

The data path must be flushed before a software resets the 82599. The recommended method to flush

the transmit data path is:

1. Inhibit data transmission by setting the HLREG0.LPBK bit and clearing the RXCTRL.RXEN bit. This

configuration avoids transmission even if flow control or link down events are resumed.

2. Set the GCR_EXT.Buffers_Clear_Func bit for 20 microseconds to flush internal buffers.

3. Clear the HLREG0.LPBK bit and the GCR_EXT.Buffers_Clear_Func.

4. It is now safe to issue a software reset.

10 Padding on Transmitted SCTP Packets

When using the 82599 to offload the CRC calculation for transmitted SCTP packets, software should not

add Ethernet padding bytes to short packets (less than 64 bytes). Instead, the HLREG0.TXPADEN bit

should be set so that the 82599 pads packets after performing the CRC calculation.

11 82599EN EEPROM Image File

The 82599EN SKU (the single-port variant of the product) requires the usage of Dev_Starter EEPROM

v4.21 or higher. Please contact your Intel representative to obtain updated EEPROM images.

12 Selecting a RX Pool Using VLAN Filters

RX Pool selection is described in 82599 Datasheet, Section 7.10.3.2. Note that pools are first selected

by MAC Address filtering, and then by VLAN filtering. If the application is aiming to map packets to

pools exclusively by their VLAN tags, it needs to replicate all incoming packets to all the different pools

by their MAC Address.

In order to achieve the packet replication, PFVTCTL. Rpl_En should be set and the relevant MAC

Address filtering bits should be set:

• MPSAR, PFUTA, MTA and VFTA tables.

• Relevant bits in PFVML2FLT registers – ROMPE, ROPE, BAM and MPE.

Pool selection by VLAN is then controlled by the PFVLVF and PFVLVFB registers.