Intel® 82599 10 Gigabit Ethernet Controller Specification Update Networking Division (ND) March 2014 Revision 3.
Intel® 82599 10 GbE Controller—Revision History Revision History Date Revision Description 9/2008 0.5 • Supports datasheet. Initial public release. 11/2008 0.6 • Supports datasheet. Updated with additional testing results. 3/2009 0.75 • Removed fixed Errata #9, #10, #23. 5/20091 1.9 • Added Errata #25 through #38. 1. Revision number changes to 1.9 at product release. No other versions have been released between revisions 0.75 and 1.9. Date Revision 7/2009 2.
Revision History—Intel® 82599 10 GbE Controller Date Revision 8/15/2011 2.81 Description Specification Clarifications added or updated: • 6. AN 1G TIMEOUT Only Works When the Link Partner Is Idle (Text in description corrected.) • 8. PCIe Timeout Interrupt (Added) • 9. Master Disable Flow (Added) Errata added or updated: • 48. FCoE: Exhausted Receive Context Is not Invalidated if Last Buffer Size Is Equal to User Buffer Size (Updated Windows* driver information in workaround.) • 50.
Intel® 82599 10 GbE Controller—Revision History Date Revision 9/5/2012 2.87 Description Specification Clarifications added or updated: • 2. PCIe Completion Timeout Value Must Be Properly Set (Last two paragraphs updated for clarity.) Specification Changes added or updated: • 5. MAC Link Setup and Auto Negotiation (Added) Errata added or updated: 6/21/13 2.9 • 55. XAUI Interface Might not Be Able to Link After a Specific Reset Sequence (Added) • 56. ETS Resolution (Added) • 57.
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Introduction—Intel® 82599 10 GbE Controller 1.0 Introduction This document applies to the Intel® 82599 10 GbE Controller. This document is an update to the Intel® 82599 10 Gigabit Ethernet Controller Datasheet. It is intended for use by system manufacturers and software developers. All product documents are subject to frequent revision and new order numbers will apply. New documents may be added. Be sure you have the latest information before finalizing your design.
Intel® 82599 10 GbE Controller—Marking Diagram Table 1-2 Device ID (Continued) Device ID Code Vendor ID Device ID 82599 (XAUI/BX4) 0x8086 0x10FC 82599 (Single Port SFI Only) 0x8086 0x1557 1.2 Marking Diagram Table 1-3 MM Numbers Product Tray MM# Tape and Reel MM# JL82599 (Lead Free) B0 Production (Performance; XAUI) 903143 903142 JL82599 (Lead Free) B0 Production (Performance; XAUI + Serial; KR/SFI) 903140 903139 JL82599EN (Single Port SFI Only); Port 1 disabled.
Nomenclature Used in This Document—Intel® 82599 10 GbE Controller 1.3 Nomenclature Used in This Document This document uses specific terms, codes, and abbreviations to describe changes, errata, sightings and/or clarifications that apply to silicon/steppings. See Table 1-4 for a description. Table 1-4 Terms, Codes, Abbreviations Name Description Specification Changes Modifications to the current published specifications. These changes will be incorporated in the next release of the specifications.
Intel® 82599 10 GbE Controller—Hardware Sightings, Clarifications, Changes, Updates, and Errata 2.0 Hardware Sightings, Clarifications, Changes, Updates, and Errata See Section 1.3 for an explanation of terms, codes, and abbreviations. Table 2-1 Summary of Hardware Sightings Hardware Sighting None Table 2-2 N/A Summary of Specification Clarifications Specification Clarification 10 Status Status 1. SFP+ Statement N/A 2. PCIe Completion Timeout Value Must Be Properly Set N/A 3.
Hardware Sightings, Clarifications, Changes, Updates, and Errata—Intel® 82599 10 GbE Controller Table 2-2 Summary of Specification Clarifications (Continued) Specification Clarification 16. SR-IOV Prefetchable Address Space Table 2-3 Status N/A Summary of Specification Changes Specification Change Status 1. PBA Number Module — Word Address 0x15-0x16 N/A 2. Updates to PXE/iSCSI EEPROM Words (B0 Stepping) N/A 3. Flow Director: Update Filter Flow Limitation N/A 4.
Intel® 82599 10 GbE Controller—Hardware Sightings, Clarifications, Changes, Updates, and Errata Table 2-5 Summary of Errata; Errata Include Steppings (Continued) Erratum 12 Status 8. Incorrect Behavior in the Switch Security Violation Packet Count (SSVPC) Statistic Register B0=Yes; NoFix 9. FCoE: To Read DMA-Rx FCoE context, CSRs Need to Add a Dummy Write B0=Yes; NoFix 10. In 100M Link Mode, CSR Access to DMA-Rx Might Reach Internal Timeout B0=Yes; NoFix 11.
Hardware Sightings, Clarifications, Changes, Updates, and Errata—Intel® 82599 10 GbE Controller Table 2-5 Summary of Errata; Errata Include Steppings (Continued) Erratum Status 30. NC-SI: Additional Multicast Packets May Be Forwarded to the BMC B0=Yes; NoFix 31. SMBus: Unread Packets Received on One Port May Cause Loss of Ability to Receive on Other Port B0=Yes; NoFix 32. NC-SI: Packet Loss When the BMC Sends Packets to Both Ports and One Port Has Its Link Down B0=Yes; NoFix 33.
Intel® 82599 10 GbE Controller—Hardware Sightings, Clarifications, Changes, Updates, and Errata Table 2-5 Summary of Errata; Errata Include Steppings (Continued) Erratum 14 Status 53. Flow Director Filters Configuration Issue B0=Yes; NoFix 54. PF's MSI TLP Might Contain the Wrong Requester ID When a VF Uses MSI-X B0=Yes; NoFix 55. XAUI Interface Might not Be Able to Link After a Specific Reset Sequence B0=Yes; NoFix 56. ETS Resolution B0=Yes; NoFix 57.
Specification Clarifications—Intel® 82599 10 GbE Controller 2.1 Specification Clarifications 1 SFP+ Statement It is important to note that the SFP+ Specification (SFF-8431) is a system level specification and performance varies as a function of a board design and connector vendor. When designing a system to meet this specification, it is important to take these system level functions into account.
Intel® 82599 10 GbE Controller—Specification Clarifications 4 Use of Wake on LAN Together with Manageability The Wakeup Filter Control Register (WUFC) contains the NoTCO bit, which affects the behavior of the wakeup functionality when manageability is in use. Note that if manageability is not enabled, the value of NoTCO has no effect. When NoTCO contains the hardware default value of 0b, any received packet that matches the wakeup filters will wake the system.
Specification Clarifications—Intel® 82599 10 GbE Controller 6 AN 1G TIMEOUT Only Works When the Link Partner Is Idle The auto-negotiation timeout mechanism (PCS1GLCTL.AN_1G_TIMEOUT_EN) only works if the 1G partner is sending idle code groups continuously for the duration of the timeout period, which is the usual case. However, if the partner is transmitting packets, an auto-negotiation timeout will not occur since auto-negotiation is restarted at the beginning of each packet.
Intel® 82599 10 GbE Controller—Specification Clarifications 9 Master Disable Flow During the “Master Disable” flow, the device driver should set the PCIe Master Disable bit and then poll the PCIe Master Enable Status bit to determine if any requests are pending. There are cases where this bit will not be released (such as flow control or link down), even if the PCIe Transaction Pending bit is cleared in the Device Status register.
Specification Clarifications—Intel® 82599 10 GbE Controller 13 82599 SFP+ Receiver Specification Conforms to SFF-8431 The 82599 SFI interface supports the electrical specification defined in the SFI+ MSA (SFF Committee SFF-8431). The 82599 SFI receiver is conformant with the SFI receiver specification, and expects the transmitted signal to comply with the SFF-8431 electrical specification listed in SFF-8431 3.51 Table 11 and Table 12.
Intel® 82599 10 GbE Controller—Specification Changes 2.2 Specification Changes 1 PBA Number Module — Word Address 0x15-0x16 Note: 2 Note: 3 This information now appears in the Intel® 82599 10 GbE Controller Datasheet, Revision 2.8 Updates to PXE/iSCSI EEPROM Words (B0 Stepping) This information now appears in the Intel® 82599 10 GbE Controller Datasheet, Revision 2.
Specification Changes—Intel® 82599 10 GbE Controller 5 MAC Link Setup and Auto Negotiation According to the 82599 Datasheet (see Section 3.7.4.2), Link is configured by setting the speed in the AUTOC.LMS field, selecting the appropriate physical interface in AUTOC.1G_PMA_PMD, AUTOC.10G_PMA_PMD_PARALLEL, and AUTOC2.10G_PMA_PMD_Serial and is completed by restarting auto-negotiation by setting AUTOC.Restart_AN to 1b.
Intel® 82599 10 GbE Controller—Documentation Updates 8 EEPROM Device Size The following EEPROM device size updates will be included in the next Datasheet release. Section 12.6.2.1 - Minimum EEPROM Sizes • No manageability - 16 KB (128 Kb) • SMBus/NC-SI - 32 KB (256 Kb) Section 12.6.2.2 - Recommended EEPROM Sizes • No manageability - 32 KB (256 Kb) • SMBus/NC-SI - 32 KB (256 Kb) Note: 9 These EEPROM device sizes are required when using dev_starter image v4.25 or later.
Errata—Intel® 82599 10 GbE Controller 2.4 Note: 1 Errata If the errata applies to a stepping, “Yes” is indicated for the stepping (for example: “B0=Yes” indicates errata applies to stepping B0). If the errata does not apply to the stepping, “No” is indicated (for example: “B0=No” indicates the errata does not apply to stepping B0).
Intel® 82599 10 GbE Controller—Errata Workaround: Software - Reset Flow Director (FD) tables when max-length indication is observed, or hold image of all the FD table and update the FD table (holding the image is less recommended). The FD table is the hardware internal memory structure. Clearing this table means that the packet buffer memory of FD is cleared and linked to the empty link-list and head/tail CSRs are initialized.
Errata—Intel® 82599 10 GbE Controller 5 Flow Director Statistics Inaccuracy Problem: FDIRMATCH should count the number of packets that matched any flow director filter. FDIRMISS should count the number of packets that missed matching any flow director filter. Implication: The counters cannot be used for exact statistics. Counters should be used as an approximate indication on miss/match of filters. Workaround: None.
Intel® 82599 10 GbE Controller—Errata 8 Incorrect Behavior in the Switch Security Violation Packet Count (SSVPC) Statistic Register Problem: During VM Migration (or other VFLR scenarios), VM-to-VM packets that should be forwarded to a VM that is currently in migration might be dropped; they may not forwarded to the VM internally and not forwarded to the network. These packets are counted both as bad packets in the SSVPC counter and also as good packets in the DMA-TX good-packet counter.
Errata—Intel® 82599 10 GbE Controller Workaround: SW - in 100 Mb/s link mode we need to disable aggregation in DMA-Rx (set RDRXCTL.AGGDIS=1) and to extend the PCIe timeout extension to 32 µs (set PCIEMISC. TO_extension to 011). When aggregation is disabled, expect an impact on performance for packets below 128B in length. Do not increase the timeout extension beyond 32µs to avoid system issues.
Intel® 82599 10 GbE Controller—Errata 13 Issues in Clock Switching of MAC Clocks Problem: During changes in the internal link-speed, the timing of the clock-switch might cause problems in the transmit path. Implication: The transmit path might hang. Workaround: In SW, set bit 19 of the AUTOC2 register to 1b as part of init flow (through EEPROM/SW). This delays the link-up flow by 10 µs, allowing a safe clock-switch. Note that Intel drivers expect bit 19 of the AUTOC2 register to be set by EEPROM.
Errata—Intel® 82599 10 GbE Controller 15 Clause 37 AN: 82599 Will not Restart AN if Receiving Invalid Idle Codes During Configuration State Problem: According to clause 37, DUT should restart AN (auto-negotiation) if it receives invalid idle codes. If the device receives bad idle codes in the configuration state of the PCSRX AN SM, it will not restart AN. Implication: Specification conformance to 1G clause 37. Workaround: None.
Intel® 82599 10 GbE Controller—Errata 18 SGMII 100M: 82599 Might Need a SW-Reset When Link-Mode Enters/Exits 100M Problem: On speed changes to or from 100 Mb and for specific traffic timing, clock switching might occur during traffic resulting in issues in TX path. Implication: When transmit path appears un-responsive following a entry/exit to 100M speed, a SW reset is required.
Errata—Intel® 82599 10 GbE Controller Workaround: Operate in BYPASS mode and avoid any 82599 output contention. Status: B0=Yes; NoFix 21 MACSec: Tx Octets Protected (LSECTXOCTP) Increment More Than Required Problem: The 82599 is required to count in this statistic the user data only. The counter currently includes bytes outside the user data (DA, SA, and SECTAG fields). Implication: Statistic does not provide the required data. Specification compliance issue. Workaround: None.
Intel® 82599 10 GbE Controller—Errata 23 ERR_COR Message TLPs Are not Sent for Advisory Errors in D3 Problem: If the 82599 is in D3 state, and if set to advisory non-fatal, an ERR_COR message is not sent for the following errors: Unexpected Completion, Poisoned TLP, Completer Abort, and Unsupported Request. Implication: The 82599 is required by the PCIe specification to send error messages for all errors caused by a received TLP when in D3hot. The 82599 violates this requirement.
Errata—Intel® 82599 10 GbE Controller Workaround: None. Status: B0=Yes; NoFix 26 82599 Might not Be Recognized by PCIe in EEPROM-Less Mode Problem: The 82599 without an EEPROM or with a blank EEPROM might not be recognized on some PCIe system implementations. This issue is not consistent and is unit/board/system sensitive. It is caused because the hardware default configuration might incorrectly start an internal PLL calibration before the PCIe reference-clock becomes stable.
Intel® 82599 10 GbE Controller—Errata 28 Re-Enabling a Port Using the Rising Edge of LAN_DIS_N Requires a LAN_PWR_GOOD Reset Problem: To re-enable a port using the rising edge of LAN_DIS_N (after it was disabled through the pin) it is required to go through a LAN_PWR_GOOD reset. PERST# (PCIe reset) cannot be used to re-enable a port. Implication: This limitation requires a cold boot in order for the LAN_DIS_N rise to take effect. Workaround: Reset the 82599 using LAN_PWR_GOOD (cold reboot).
Errata—Intel® 82599 10 GbE Controller Implication: Additional packets might be forwarded to the BMC. Workaround: BMC should filter the different multicast packets. Status: B0=Yes; NoFix 31 SMBus: Unread Packets Received on One Port May Cause Loss of Ability to Receive on Other Port Problem: The device’s two ports share an internal memory. When packets are received by one of the ports and not read by the BMC, they are stored in the shared memory.
Intel® 82599 10 GbE Controller—Errata 33 The EEPROM Core Clocks Gate Disable Setting Impacts Link Status During D3 State Problem: Setting EEPROM bit Core Clocks Gate Disable has side effects when both manageability and Wake on LAN (WoL) are disabled for a port. The Link and LEDs are both active in D3 when they should be disabled. The Core Clocks Gate Disable bit is set in the 82599's manageability EEPROM images. Starting from EEPROM Dev Starter, Revision 4.25 and later it is set for all images.
Errata—Intel® 82599 10 GbE Controller Workaround: Keep a dummy Tx queue active in a reserved, lowest priority TC, transmitting packets that are dropped by an internal IOV related configuration (requires partial internal IOV configuration. Does NOT require real IOV). This avoids an empty condition, which avoids the issue. Status: B0=Yes; NoFix 35 SR-IOV: PCIe Capability Structure in VF Area Is Incorrectly Implemented Problem: SR-IOV Specification 1.0 section 3.5, 3.5.2, 3.5.3, 3.5.6, and 3.5.
Intel® 82599 10 GbE Controller—Errata 37 PCIe: PM_Active_State_NAK Message Might Be Ignored Problem: A PM_Active_State_NAK message received by the 82599 might be ignored under the following conditions: • The 82599 configuration for ASPM L1 is enabled, and L0s is disabled. Note that this configuration is possible only if an upstream device also supports ASPM L1. • The 82599 initiates APSM L1 transition by sending PM_Request_L1 DLLPs upstream.
Errata—Intel® 82599 10 GbE Controller 38 PCIe: Incorrect PCIe De-emphasis Level Might Be Reported Problem: Current De-emphasis Level status bit in the Link Status 2 register in the PCIe configuration space should reflect the level of de-emphasis configured by the upstream device. By default, this bit shows the correct status of -6 db. If the upstream device requests the change of deemphasis during link training according to the PCIe 2.0 specification, the status shows correctly the change to -3.5 db.
Intel® 82599 10 GbE Controller—Errata Workaround: If a system is requested to operate under this specific scenario, a custom EEPROM image can be provided to clear the WUS register each time it is set. Note: A custom EEPROM image can be provided to workaround this issue. To obtain a custom EEPROM image, contact your Intel representative. Status: B0=Yes; NoFix 40 PME_Status Might Fail to Report a Wake-Up Event Problem: During a wake-up event, the PME_Status bit is set in both PMCSR and WUC registers.
Errata—Intel® 82599 10 GbE Controller 42 PCIe: 82599 Transmitter Does not Enter L0s Problem: According to the PCIe specification “Ports that are enabled for L0s entry must transition their transmit lanes to the L0s state if the defined idle conditions are met for a period of time not to exceed 7 s”. Due to how the 82599 was designed, the idle counter does not initiate a L0s transition. Implication: PCIe specification compliance issue.
Intel® 82599 10 GbE Controller—Errata 44 Header Splitting Can Cause Unpredictable Behavior Problem: Header Splitting mode (SRRCTL.DESCTYPE=010b or 101b and PSRTYPE[11:0]≠0) might cause unpredictable behavior and should not be used. Implication: Unpredictable behavior. Workaround: Header Splitting should not be enabled. Starting with Intel® driver Release 16.0, Header Splitting cannot be enabled.
Errata—Intel® 82599 10 GbE Controller 46 PCIe: Correctable Errors Reported When Using Rx L0s in a x1 Configuration Problem: When using Rx L0s in an x1 configuration, the 82599 reports receiver errors at a rate of more than one per minute on some platforms. Implication: Correctable errors are reported at a higher rate than can be explained by random bit errors. These errors should be ignored by the system. Workaround: None.
Intel® 82599 10 GbE Controller—Errata 48 FCoE: Exhausted Receive Context Is not Invalidated if Last Buffer Size Is Equal to User Buffer Size Problem: If the last buffer of an FCoE context doesn’t have sufficient room for the FC payload, the context is considered exhausted and must be invalidated by hardware. The FCoE context is not invalidated as required under the following scenarios: • FCoE last buffer size (FCDMARW.LASTSIZE) equals the exact user buffer size (FCBUFF.BUFFSIZE).
Errata—Intel® 82599 10 GbE Controller 49 KR TXFFE Coefficient Update Is not Possible if Middle Coefficient Is at Maximum Value Problem: During the KR interface startup sequence, the link partner may request the PRESET setting of the TXFFE coefficients, which sets the maximum value of the middle coefficient c(0). The coefficients are set correctly, but further requests to adjust the coefficients will fail. The condition is indicated by the “max, max, max” status response.
Intel® 82599 10 GbE Controller—Errata 51 LEDs Cannot Be Configured to Blink in LED_ON Mode Problem: When the LEDx_Mode field of a specific LED is set to 1110b in the LEDCTL register (0x00200), the respective LED is in LED_ON mode. This LED should be always asserted when the mode is set to LED_ON. The LED should also blink based on the LEDx_BLINK setting; however, due to a device limitation, the LED does not blink regardless of the LEDx_BLINK value.
Errata—Intel® 82599 10 GbE Controller Workaround: If RXCTRL.RXEN is clear, set SECRXCTL.RX_DIS and wait for a SECRXSTAT.SECRX_RDY indication before configuring the flow director filters. This workaround is implemented in the Intel ixgbe driver 3.8.
Intel® 82599 10 GbE Controller—Errata Workaround: This issue is resolved by the 82599 EEPROM Dev Starter rev 4.22 or newer. Status: B0=Yes; NoFix 56 ETS Resolution Problem: IEEE802.1Qaz specification, aka Enhanced Transmission Selection (ETS) for Bandwidth Sharing Between Traffic Classes, requires ETS resolution of 1% with max allowed deviation of +/- 10% of link bandwidth. ETS resolution is defined as the minimum percent of link bandwidth that can be allocated to a specific traffic class.
Errata—Intel® 82599 10 GbE Controller 58 82599 LAN Port #1 SFI Link Instability Problem: If the PCIe Function #0 is moved to D3 state, it might affect the link of Port #1. For example, when the Windows driver is disabled for this function. This issue might happen only under the following conditions: • Both ports are configured to SFI Link mode. • Manageability is not enabled. • APM (WoL) is not enabled. • Port #0 has no link before disabled. Implication: Port #1 link instability.
Intel® 82599 10 GbE Controller—Errata 60 IPv4 Checksum Error Might Be Reported for Multicast Frames Over 12 KB Problem: IPE (IPv4 Checksum Error) might rarely be set in the Rx descriptor of multicast frames over 12 KB even though their checksum is valid. Implication: An IPE (IPv4 Checksum Error) error can incorrectly be reported by the 82599. Workaround: To avoid the erratum condition, limit the size of jumbo frames to less than or equal to 12 KB.
Errata—Intel® 82599 10 GbE Controller 62 Flow Director: Collision Indication Can Be Cleared by Adding a New Filter Problem: A Flow Director collision indication of the last Signature filter can be unintentionally cleared by adding a subsequent Signature filter. Implication: Flow Director collision indication is missing. Workaround: None. Status: B0=Yes; NoFix 63 Clearing RXEN During VM-to-VM Loopback Traffic Might Cause Rx Hang Problem: If the RXCTRL.
Intel® 82599 10 GbE Controller—- Software Clarifications 3.0 Table 3-1 - Software Clarifications Summary of Software Clarifications Software Clarification Status 1. While in TCP Segmentation Offload, Each Buffer Is Limited to 64 KB N/A 2. RSC Performance Tradeoff N/A 3. Serial Interfaces Programmed by Bit Banging N/A 4. Identify Network Adapter Port by Blinking LED N/A 5.
- Software Clarifications—Intel® 82599 10 GbE Controller 3 Serial Interfaces Programmed by Bit Banging When bit-banging on a serial interface (such as SPI, I2C, or MDIO), it is often necessary to perform consecutive register writes with a minimum delay between them. However, simply inserting a software delay between the writes can be unreliable due to hardware delays on the CPU and PCIe interfaces.
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