Datasheet

Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet 95
Table 54. Input/Output Signals (Single Driver)
Name Active Level Clock Signal Group Qualified
A[35:3]# Low BCLK System Bus ADS#, ADS#+1
ADS# Low BCLK System Bus Always
AP[1:0]# Low BCLK System Bus ADS#, ADS#+1
BREQ0# Low BCLK System Bus Always
BP[3:2]# Low BCLK System Bus Always
BPM[1:0]# Low BCLK System Bus Always
D[63:0]# Low BCLK System Bus DRDY#
DBSY# Low BCLK System Bus Always
DEP[7:0]# Low BCLK System Bus DRDY#
DRDY# Low BCLK System Bus Always
LOCK# Low BCLK System Bus Always
REQ[4:0]# Low BCLK System Bus ADS#, ADS#+1
RP# Low BCLK System Bus ADS#, ADS#+1
RS[2:0]# Low BCLK System Bus Always
TRDY# Low BCLK System Bus Response phase
Table 55. Input/Output Signals (Multiple Driver)
Name Active Level Clock Signal Group Qualified
AERR# Low BCLK System Bus ADS#+3
BERR# Low BCLK System Bus Always
BINIT# Low BCLK System Bus Always
BNR# Low BCLK System Bus Always
HIT# Low BCLK System Bus Always
HITM# Low BCLK System Bus Always
PICD[1:0] High PICCLK APIC Always